Selectable-Precision Biquad Feedback for Quantization-Sensitive Filters
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Solution Overview
Problem
Digital signal processing systems face bit quantization-related performance issues due to fixed bit precision constraints, which can lead to adverse effects in biquad stage performance, particularly when dealing with transfer functions sensitive to bit quantization effects.
Innovation Solution
Implementing biquad stages with selectable bit precision feedback paths, where the bit precision is dynamically adjusted based on performance metrics and coefficients to mitigate bit quantization effects, ensuring optimal performance across all available biquad stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed bit precision is used in biquad stages, then device complexity is reduced and ease of manufacture is improved, but bit quantization-related performance issues occur and reliability deteriorates
Solution Approach 1:
The patent implements dynamic bit precision adjustment in feedback paths of biquad stages. The bit precision is made variable rather than fixed, allowing the system to adapt to different transfer function requirements. This dynamic adjustment resolves the contradiction by enabling high reliability for sensitive transfer functions while maintaining simpler fixed precision for less sensitive cases, thus improving overall reliability without permanently increasing device complexity.
Solution Approach 2:
The patent changes the bit precision parameter of feedback paths based on the specific transfer function being implemented. By allowing the bit precision parameter to vary according to the application requirements, the system can achieve high performance for sensitive transfer functions while avoiding unnecessary complexity for less sensitive applications. This parameter change approach directly addresses the contradiction between reliability and device complexity.
2Reliability
If higher bit precision is used in all feedback paths, then bit quantization effects are reduced and performance is improved, but device complexity and resource requirements increase
Solution Approach 1:
The patent applies different bit precision levels to different feedback paths within the biquad stage based on their specific requirements. Rather than uniformly applying high precision to all paths, the system selectively increases precision only where needed for sensitive transfer functions. This local quality approach resolves the contradiction by improving reliability only where necessary while avoiding the device complexity and resource overhead of universal high precision.
Solution Approach 2:
The patent makes bit precision dynamically adjustable per feedback path rather than fixed uniformly across all paths. This allows the system to allocate higher precision resources dynamically to specific feedback paths that require them for accurate transfer function implementation, while keeping other paths at lower precision levels. This dynamic allocation resolves the contradiction between reliability and device complexity by optimizing resource usage.
3Adaptability or versatility
If selectable bit precision feedback paths are implemented, then adaptability to different transfer functions is improved, but device complexity increases
Solution Approach 1:
The patent implements selectable bit precision feedback paths that can be dynamically configured based on the transfer function being implemented. The precision selection logic allows the system to adapt to different transfer function requirements by choosing appropriate precision levels for each feedback path. This dynamic selectability resolves the contradiction by providing high adaptability for various transfer functions while managing device complexity through structured selection mechanisms rather than completely arbitrary configuration.
Data Source
AI summary
An apparatus includes a plurality of delay elements, a plurality of multipliers and an accumulator to form a biquad stage; and a precision logic circuit. The biquad stage includes feedback paths; at least one feedback path has an adjustable bit precision; and the precision logic is adapted to regulate the bit precision of the feedback path(s) based at least in part on at least one parameter that is associated with the biquad stage.