Biquad Filter Arithmetic for Low-Power High-Precision IIR Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital signal processing systems for high-order IIR filters face errors due to finite binary word lengths, particularly in biquad implementations, leading to calculation noise, DC-toggling effects, and challenges with low cutoff frequencies and high sampling frequencies.
Innovation Solution
The implementation of a hybrid floating-point and fixed-point arithmetic system that scales binary coefficients using values close to {−2, −1, 0, 1, 2}, allowing for low binary precision representation and shifting operations, which provides precision better than single or double precision floating-point arithmetic with minimal power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional fixed-point arithmetic with short coefficient words is used, then power consumption is low, but precision is insufficient leading to calculation noise and DC-toggling effects
Solution Approach 1:
The patent transforms the coefficient representation by adding an offset (typically 2 or 4) to the conventional fixed-point coefficients. This parameter change shifts the coefficient values away from zero, enabling the use of fewer fractional bits while maintaining precision. The transformed coefficients are stored in a modified format that reduces the word length required, thereby lowering power consumption without sacrificing filter precision.
Solution Approach 2:
The patent segments the coefficient representation into an integer part (offset value) and a fractional part. The integer part is handled separately through preprocessing, while only the fractional part needs to be stored and processed in the filter. This segmentation allows the system to achieve high precision with reduced word length for the stored coefficients, reducing power consumption.
2Measurement precision
If floating-point arithmetic is used to improve precision, then calculation noise is reduced, but computational cost and power consumption increase significantly
Solution Approach 1:
The patent uses a simplified arithmetic approach that sacrifices the full flexibility of floating-point arithmetic but achieves comparable precision for the specific application of IIR filter coefficients. The modified fixed-point arithmetic with offset coefficients provides precision similar to floating-point at a fraction of the computational cost, effectively using a 'cheaper' arithmetic method that is sufficient for this specific purpose.
Solution Approach 2:
By changing the parameter representation (adding offset to coefficients), the patent enables the use of simpler fixed-point arithmetic operations that achieve precision comparable to floating-point arithmetic. The transformed coefficients allow standard fixed-point arithmetic units to operate with reduced word length while maintaining the precision benefits typically associated with floating-point arithmetic.
3Reliability
If high sampling frequency is used with low cutoff frequency, then filtering performance is improved, but errors due to finite binary word length increase
Solution Approach 1:
The patent performs preliminary transformation of the filter coefficients before they are used in the filter implementation. By pre-calculating and storing the offset coefficients in the modified format, the system prepares the coefficients in advance to handle the precision requirements of high sampling frequency operation. This preliminary action ensures that when the filter operates at high sampling frequencies, the coefficients are already optimized to minimize quantization errors.
Data Source
AI summary
Biquad stage systems and methods include receiving at biquad sections a signal sample, generating, by each biquad section, a pair of output values based on the signal sample, including a first value based on fixed-point processing path and a second value emulating a floating-point processing path, and accumulating the pair of output values from each of the plurality of biquad sections to generate an output signal. The biquad stage receives an N-bit input signal, which is processed by a biquad section. Delay elements delay the signal sample before input to other biquad sections. The delayed signal sample is input to the first processing path and the second processing path of a corresponding biquad stage. By performing the processing based on two paths, a more accurate result can be found when using a reduced word length in the multiply operations resulting in a lowering of the power consumption.