BiQuad Filter Shift-Add Approximation for Low-Power Multiplication
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Solution Overview
Problem
BiQuad filters require significant hardware resources and power due to floating-point multiplication operations, which are computationally expensive and inefficient in digital systems.
Innovation Solution
Approximating multiplication operations using bit-wise shift operations and additions, replacing floating-point multiplications with no-cost bit-wise rewiring and fixed-point arithmetic, thereby reducing hardware usage and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If floating-point multiplication operations are used in BiQuad filter, then calculation precision is maintained, but hardware resources and power consumption increase significantly
Solution Approach 1:
The patent changes the parameter representation from floating-point to fixed-point arithmetic, and replaces multiplication operations with shift and addition operations. This parameter transformation maintains sufficient calculation precision for filter applications while dramatically reducing power consumption and hardware resource requirements.
Solution Approach 2:
The patent replaces expensive floating-point multiplication units with cheaper fixed-point arithmetic units that use shift and addition operations. These simpler computational units consume less power and occupy fewer hardware resources, achieving a cost-effective solution that sacrifices minimal precision for significant resource savings.
2Measurement precision
If floating-point multiplication operations are used in BiQuad filter, then accurate coefficient application is achieved, but hardware complexity and computation cycles increase
Solution Approach 1:
The patent transforms the computational parameters from floating-point to fixed-point representation and replaces multiplication with shift-add operations. This parameter change simplifies the hardware architecture by eliminating complex multiplier circuits while maintaining adequate coefficient application accuracy for digital filter operations.
Solution Approach 2:
The patent substitutes complex mechanical-like floating-point multiplication operations with simpler fixed-point shift and addition operations. This substitution replaces hardware multipliers with basic arithmetic logic units, reducing device complexity and computation cycles while preserving essential filter functionality.
3Reliability
If floating-point multiplication operations are used in BiQuad filter, then precise signal processing is achieved, but hardware resources and computation time increase
Solution Approach 1:
The patent changes the arithmetic parameters from floating-point to fixed-point and replaces multiplication with shift-add operations. This parameter transformation maintains signal processing accuracy sufficient for most applications while dramatically improving computation efficiency by reducing the number of computational cycles required.
Solution Approach 2:
The patent replaces resource-intensive floating-point multiplication units with simpler fixed-point arithmetic units using shift and addition. This substitution improves productivity by enabling faster computation with fewer hardware resources, achieving a practical balance between signal processing reliability and computational efficiency.
Data Source
AI summary
A filter is disclosed. The filter includes at least one first multiplication approximation unit, for approximating at least one first multiplication operation corresponding to at least one first coefficient with at least one first bit-wise shift operation; and at least one second multiplication approximation unit, for approximating at least one second multiplication operation corresponding to at least one second coefficient with a plurality of second bit-wise shift operations and at least one addition operation.