Biquad IIR Filter Core With Coefficient Switching for Low-Latency Timing
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Solution Overview
Problem
Biquad filters used for digital audio signal processing face limitations in processing speed due to the timing of the critical feedback path, which is often set by the delay of the first multiplier, leading to inefficient use of multipliers when latency exceeds one clock cycle.
Innovation Solution
A biquad core with five multiplier elements, each including a multiplier, a first delay element, and a second delay element, along with multiplexers that switch between two different coefficients on each clock cycle, allowing for efficient processing by synchronizing signal timing and utilizing resources effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the feedback path timing is set by the delay of the first multiplier, then the filtering function is achieved, but the processing speed is limited and multipliers are not efficiently used when latency exceeds one clock cycle
Solution Approach 1:
The patent segments the feedback path by introducing intermediate storage elements that divide the delay into discrete one-clock-cycle stages. This allows the feedback signal to be properly timed without limiting the overall processing speed of the filter, as each segment can operate independently at the full clock rate
Solution Approach 2:
The patent introduces intermediate storage elements as mediators between the multipliers in the feedback path. These intermediaries buffer the signals, allowing each multiplier to operate at full speed while maintaining the correct timing relationships in the feedback loop
2Productivity
If multipliers with latency more than one clock cycle are used, then the filtering function is achieved, but some multipliers are not efficiently used
Solution Approach 1:
The patent implements periodic switching of coefficient sets synchronized with the clock cycles. This allows the system to use standard-latency multipliers efficiently by coordinating their operation with periodic coefficient updates, ensuring all multipliers are actively used each cycle without complex timing requirements
Data Source
AI summary
Embodiments of An apparatus and method are disclosed. In an embodiment, an apparatus for performing digital infinite impulse response filtering includes a biquad core that includes five multiplier elements, each multiplier element including, a multiplier, a first delay element in series with and after the multiplier, and a second delay element in series with and after the first delay element, and a multiplexer associated with each of the five multiplier elements, each multiplexer configured to provide one of at least two different coefficients to the multiplier of the corresponding multiplier element.