Branch Information Storage Entry Sharing Across Threads
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Solution Overview
Problem
In data processing systems, especially those with fine-grained multithreading, the branch information storage faces pressure due to varying address translation regimes across threads, leading to a proliferation of entries required for efficient branch instruction detection.
Innovation Solution
The proposed solution involves a processor with fetch circuitry and address translation circuitry that allocates branch information storage entries based on shared address translation regimes across threads, allowing entries to be marked as valid for multiple threads if their regimes are shared, thereby reducing the need for duplicate entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate branch information storage entries are provided for each thread, then branch instruction detection accuracy is improved, but branch information storage pressure increases
Solution Approach 1:
The patent merges branch information storage entries across multiple threads by allowing a single entry to be shared among threads that use the same address translation regime. The allocation circuitry determines whether an entry can be shared by checking if the address translation regime is common to multiple threads, thereby combining what would traditionally be separate thread-specific entries into shared entries that reduce overall storage pressure while maintaining detection accuracy for threads using the same regime.
Solution Approach 2:
The patent makes branch information storage entries universal by enabling them to serve multiple threads simultaneously. An entry allocated for one thread can also be accessed by other threads if they share the same address translation regime, as determined by the allocation circuitry. This multi-functionality allows a single entry to fulfill the branch detection need for multiple threads, reducing the total number of entries required.
2Quantity of substance
If branch information storage entries are shared across threads, then storage efficiency is improved, but branch instruction detection accuracy may deteriorate
Solution Approach 1:
The patent applies local quality by making entry sharing conditional on the address translation regime. Rather than universally sharing all entries or keeping them completely separate, the allocation circuitry evaluates each entry's applicability to specific threads based on their address translation regime. Entries are shared locally among threads with matching regimes while remaining exclusive to threads with different regimes, thus maintaining detection accuracy within each regime group while improving overall storage efficiency.
3Measurement precision
If thread-specific branch information storage is implemented, then detection precision is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the allocation circuitry to automatically determine whether branch information storage entries can be shared across threads. The circuitry autonomously evaluates the address translation regime of the current thread and compares it with existing entries, making sharing decisions without requiring external intervention or complex manual management. This self-service mechanism simplifies the overall system by automating what would otherwise be a complex management task.
Solution Approach 2:
The patent uses feedback by having the allocation circuitry continuously monitor and evaluate the address translation regime of executing threads to make real-time decisions about entry allocation and sharing. The system feedbacks information about regime compatibility to the allocation logic, which then adjusts entry sharing status accordingly, ensuring detection precision is maintained while optimizing storage usage based on current thread execution context.
Data Source
AI summary
A processor fetches instructions from a plurality of threads. Each entry in a branch information storage (BIS) stores a virtual address ID for a branch, information about the branch, and thread ID information. The BIS is accessed using a virtual address of an instruction to be fetched for a thread to determine whether a hit exists, and if so, to obtain the branch information stored in the entry that gave rise to the hit. The virtual address is converted into a physical address, and an address translation regime is specified for each thread. When allocating an entry into the BIS, allocation circuitry determines, for a branch instruction for a current thread, whether the address translation regime is shared by plural threads. If so, the allocation circuitry identifies both the current thread and any other thread for which the address translation regime is shared.