Built-in Self-Test Unit Emulation Mode for Cache Tag View Access
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Solution Overview
Problem
Debugging integrated circuits, particularly in relation to cache memory, is challenging due to the lack of secure access to cache tag views, which complicates the debugging process and limits the effectiveness of built-in self-test methods.
Innovation Solution
An integrated circuit with a built-in self-test unit that reads cache tag bits and outputs them via an external interface, allowing secure access through an emulation mode, enabling the CPU or tester to read and utilize these tags for debugging purposes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If built-in self test is used to test integrated circuits, then testing capability is improved, but access to cache tag views remains restricted and debugging becomes difficult
Solution Approach 1:
The patent introduces an intermediary mechanism (emulation mode with configuration register reads) that mediates between the built-in self test unit and the cache tag views. This allows controlled access to tag bits through a defined interface without compromising the security or integrity of the cache structure, resolving the contradiction between testing capability and ease of access to cache tags.
2Reliability
If cache security is maintained, then data integrity is improved, but debugging capability deteriorates due to inability to access tag views
Solution Approach 1:
The patent implements preliminary action by establishing an emulation mode and configuration register structure before actual debugging operations. This preliminary setup creates a controlled environment where tag views can be accessed securely during testing without compromising data integrity during normal operation, thus resolving the contradiction between security and debugging capability.
3Ease of operation
If built-in self test unit reads cache tag bits, then debugging capability is improved, but access control and security mechanisms become more complex
Solution Approach 1:
The patent applies segmentation by dividing the access control mechanism into distinct segments: emulation mode activation, configuration register access, and tag bit reading. This modular approach manages complexity by breaking down the access control function into manageable parts, each with specific purposes and control logic, thereby improving debugging capability while controlling the increase in device complexity.
Data Source
AI summary
A built-in self test unit reads tag bits of a predetermined cache entry and outputs these tag bits via an external interface. The built-in self test unit enters an emulation mode upon receipt of an emulation signal via the external interface when a first configuration register has a predetermined state. The built-in self test unit then reads tag bits upon each memory mapped read of a second configuration register. The read operation advances to next sequential tag bits upon each memory mapped read of the second configuration register. The tag bits include at least one valid bit and at least one dirty bit. The tag bits also include the most significant bits of the cached address.