Bi-Sn Solder Bump Electromigration for Thermal Stability
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Solution Overview
Problem
High-speed semiconductor elements with low-K materials face challenges in thermal distortion during joining due to the low melting point of conventional lead-free solders, leading to re-melting issues during temperature cycle tests, which compromises the reliability of electronic devices.
Innovation Solution
A semiconductor device with a solder bump structure comprising a Bi-Sn alloy, featuring a first interface layer, a second interface layer, a first intermediate region with high Bi concentration, and a second intermediate region with high Sn concentration, formed by applying a direct current to induce electromigration, increasing the melting point beyond the original Sn-Bi solder temperature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If eutectic Sn-Bi solder with melting point of 139°C is used to reduce thermal distortion during joining, then joining temperature can be reduced to protect low-K materials, but the solder may re-melt during temperature cycle tests or high temperature exposure at 150°C
Solution Approach 1:
The patent changes the compositional parameters of the solder bump by creating a non-uniform distribution of Sn and Bi elements through electromigration. The solder bump is transformed from a homogeneous Sn-Bi alloy into a structured composite with Sn-rich interface layers and Bi-rich intermediate regions, thereby increasing the melting point from 139°C to above 215°C while maintaining low joining temperature benefits
Solution Approach 2:
The patent creates a composite structure within the solder bump consisting of multiple phases: Sn-rich interface layers (Cu6Sn5, Cu3Sn), Bi-rich intermediate regions, and Sn-rich intermediate regions. This composite microstructure combines the low melting point advantage of Sn-Bi solder with the high temperature stability of Sn-rich phases, resolving the contradiction between low joining temperature and high reliability
2Reliability
If conventional Sn-Ag-Cu solder with melting point of 217°C is used to ensure high temperature stability, then reliability during temperature cycle tests is improved, but thermal distortion increases during joining due to high joining temperature
Solution Approach 1:
The patent applies electromigration treatment after solder bump formation to preliminarily create a non-uniform compositional distribution before final cooling. This preliminary action of redistributing Sn and Bi elements during the molten state results in a structured solidification process that produces Sn-rich interface layers with high melting point, thereby achieving high temperature stability without requiring high joining temperatures
3Speed
If low-K materials such as porous silica are used to reduce parasitic capacitance for high-speed operation, then signal transmission speed is improved, but mechanical strength decreases making the materials vulnerable to thermal distortion
Solution Approach 1:
The patent introduces Sn-rich interface layers as intermediary regions between the copper connection pads and the solder matrix. These Sn-rich layers act as protective intermediaries that bond strongly to copper and provide mechanical support to the low-K interlayer insulation materials during thermal processes, thereby protecting the mechanically vulnerable low-K materials without affecting signal transmission performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The modified solder bump structure maintains stable electrical and mechanical connections under elevated temperatures, suppressing resistance increase and ensuring reliable performance through a higher melting point, even when subjected to temperature cycle tests and high-temperature exposure.
Implementation Method 1
formed by applying a direct current to induce electromigration
Data Source
AI summary
A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on which a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.