Built-in Self-test Circuit Memory Storage for ATE Testing
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Solution Overview
Problem
The internal memory space of Automatic Test Equipment (ATE) is insufficient for storing defect and repair information of memories during testing, leading to suspended tests, increased costs, and limited test speed, especially when testing complex IC products with larger bit widths and higher complexity.
Innovation Solution
A memory test method utilizing a built-in self-test circuit that acquires defect information, generates repair information, and stores it in a second memory, thereby expanding the storage space for repair information and allowing for faster testing without relying on the ATE's internal memory, enabling the testing of an entire wafer in one touch-down operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the internal memory space of ATE is increased to store defect and repair information, then the storage capacity is improved, but the test cost increases significantly
Solution Approach 1:
The patent extracts the storage function from the ATE system and relocates it to the DUT's internal memory. The ATE only needs to store minimal test control information, while defect information and repair information are stored in the DUT's internal memory space, eliminating the need for expensive ATE memory expansion
Solution Approach 2:
The patent creates a copy of the storage function by using the DUT's internal memory as an external storage extension for the ATE. The repair information is generated by the ATE but copied to and stored in the DUT's internal memory, allowing the ATE to function with minimal internal memory
2Quantity of substance
If the internal memory space of ATE is increased to store defect and repair information, then the storage capacity is improved, but the test time increases due to suspended tests
Solution Approach 1:
The patent performs preliminary action by allocating and preparing the internal memory space in the DUT before the actual testing begins. The memory is configured to store defect information and repair information in advance, eliminating the need for suspended tests and multiple test cycles to accommodate storage limitations
3Productivity
If high-rate compression testing is used to overcome memory limitations, then the test speed is improved, but the repair capability is lost and yield decreases
Solution Approach 1:
The patent introduces an intermediary mechanism - the internal memory of the DUT - that enables both high-speed testing and repair capability. This intermediary storage space allows the ATE to operate at high rates while still capturing and storing defect information for subsequent repair operations, bridging the gap between speed and reliability
4Quantity of substance
If the bit width of DRAM is increased to improve memory capacity, then the storage capability is improved, but the test complexity increases and cannot be completed in one touch-down operation
Solution Approach 1:
The patent segments the storage function into two parts: minimal test control information stored in ATE and bulk defect/repair information stored in DUT internal memory. This segmentation allows the system to handle high-bit-width DRAM efficiently, as the ATE only manages small control data while the DUT handles the large volume of defect and repair information
Data Source
AI summary
Embodiments of the present disclosure provide a memory test method and a device thereof, an electronic device, and a computer-readable storage medium, which relate to the field of semiconductor device testing technologies. The method is executed by a built-in self-test circuit and includes: acquiring defect information of a first memory by testing the first memory; acquiring repair information of the first memory based on the defect information of the first memory; and storing the repair information of the first memory in a second memory.