Integrated Circuit BIST for 1R1W-RAM Testing

The test control circuit is designed to serve dual purposes: it can test both 1RW-RAM (single port) and 1R1W-RAM (dual port) structures using the same circuit architecture. The circuit achieves this by implementing a virtual port mechanism where the second port's address and data are generated internally from the first port's inputs, eliminating the need for separate dedicated test control circuits for each RAM type.

Instead of providing physical duplicate signal lines for the second port, the patent creates virtual copies by generating the second port's address and data signals through address generation logic and data copying logic. This allows the test control circuit to simulate a dual-port environment using a single physical port's signal lines, thereby reducing circuit complexity while maintaining full testing capability.

The patent creates virtual copies of address and data signal lines through logical generation rather than physical duplication. The address generation logic produces the second port's address from the first port's address, and the data copying logic replicates the first port's data as the second port's data. This approach enables simultaneous read-write testing while using the same physical signal lines, thereby avoiding an increase in wire count.

The patent introduces intermediary logic blocks (address generation logic and data copying logic) that mediate between the single physical port and the virtual dual-port structure. These intermediaries transform the single port's signals into the appropriate signals for simultaneous read and write operations, eliminating the need for separate physical signal lines while enabling full dual-port functionality.

The simplified test control circuit achieves multi-functionality by implementing a virtual port mechanism that allows a single circuit design to test both 1RW-RAM and 1R1W-RAM structures. The address generation logic and data copying logic enable the circuit to simulate dual-port operations when testing 1R1W-RAM, while automatically adapting to single-port operations for 1RW-RAM, all without requiring additional hardware or increasing manufacturing complexity.

The patent utilizes parameter changes in the control signals to switch between different testing modes. By modifying the control logic based on the detected RAM type (1RW or 1R1W), the same physical circuit can dynamically adjust its behavior to provide either single-port or dual-port testing functionality, maintaining manufacturing simplicity while achieving operational versatility.