BIST Address Generation for Memories With Different Column Multiplexers
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Solution Overview
Problem
Existing methods for simultaneously testing multiple embedded memories with different column multiplexers using a single Built-In Self Testing (BIST) controller face challenges such as incomplete testing of memory locations, duplication of effort, and increased chip area requirements, leading to inefficiencies and higher manufacturing costs.
Innovation Solution
A method that selects a primary memory with the largest column multiplexer, extends the address-width register to generate extended width addresses, and uses these addresses to test secondary memories, ensuring all memory locations are tested once while maintaining the correct address sequence, thereby reducing chip area and testing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential testing of multiple embedded memories is performed using a single BIST controller, then testing completeness is improved, but testing time increases significantly
Solution Approach 1:
The patent segments the address generation process by creating separate address generation units for each memory device being tested. Each AGLU generates addresses independently for its associated memory, allowing simultaneous testing of multiple memories without address conflicts or sequential delays.
Solution Approach 2:
The patent introduces a new dimensional approach by using multiple parallel address generation units operating simultaneously, transforming the sequential single-threaded address generation into a multi-threaded parallel system, thereby reducing testing time while maintaining completeness.
2Productivity
If multiple address registers are used for each memory to enable simultaneous testing, then testing speed is improved, but chip area increases significantly
Solution Approach 1:
The patent creates a universal address generation unit that can serve multiple memory devices. Each AGLU is designed to be configurable and adaptable, generating addresses for different memory sizes and configurations, thereby reducing the need for dedicated address registers for each memory and minimizing chip area usage.
Solution Approach 2:
The patent employs parameter-configurable address generation units that can adjust their address width and generation patterns based on the specific memory being tested. This flexibility allows a single AGLU design to handle multiple memory configurations, reducing the total number of address registers needed while maintaining high testing speed.
3Device complexity
If a single BIST controller is used for multiple memories, then device complexity is reduced, but address generation efficiency decreases
Solution Approach 1:
The patent merges multiple address generation functions into a single integrated BIST controller by incorporating multiple address generation units (AGLUs) within one controller architecture. This allows the controller to manage multiple memories simultaneously, maintaining low device complexity while improving address generation efficiency through parallel operation of the AGLUs.
Data Source
AI summary
The invention discloses a method and a system for optimizing address generation for simultaneously running proximity-based Built-In-Self-Test (BIST) algorithms. The method also describes simultaneously testing proximity-based faults for different memories having column multiplexers of different sizes using the BIST algorithms. The system described above may be embodied in the form of a Built-In-Self-Test (BIST) controller. Further, the method includes selecting a memory having the largest size of column multiplexer (CMmax). After selecting the memory, size of an address-width register is extended to form an extended address-width register. Thereafter, an extended width address is generated using the extended address-width register and the extended width address is used to generate addresses for the memories. After generating the addresses, read and write operations are performed on the memories based on pre-defined rules, wherein the read and write operations provide testing of the memories.