BIST for Clock Generation Circuitry Test Coverage
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Solution Overview
Problem
Current integrated circuit designs face challenges in achieving sufficient test coverage for clock generation logic due to lack of controllability and observability, making it difficult to ensure higher quality devices through regular Automatic Test Pattern Generation (ATPG) and logic Built In Self Test (BIST).
Innovation Solution
The implementation of BIST circuitry that uses scan chains fed with pseudo-random test patterns, alternating between scan shift and capture phases, along with clock gating elements and MUXes, to enhance test coverage and deterministic fault coverage in clock generation circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If regular ATPG and logic BIST are used for clock generation circuitry, then test coverage is limited, but device complexity increases with additional test infrastructure
Solution Approach 1:
The clock generation circuitry performs self-testing by utilizing its own operational clocks to drive scan chains and validate its functionality. The circuit tests itself without requiring external test pattern generation, achieving high test coverage while avoiding additional test infrastructure complexity
Solution Approach 2:
The operational clock signals serve dual purposes: they function as normal operating clocks for circuit operation and simultaneously serve as test stimuli for validating clock generation logic. This multi-functionality eliminates the need for separate test clocks or test infrastructure
2Difficulty of detecting and measuring
If scan chains are used for testing clock division logic, then observability improves, but test time increases due to sequential scanning
Solution Approach 1:
The test methodology employs periodic alternating phases between scan shift mode and capture mode. During capture mode, multiple clock cycles are accumulated simultaneously, and during scan shift mode, results are transferred. This periodic action enables parallel data collection that reduces overall test time compared to purely sequential scanning
Solution Approach 2:
Test patterns are pre-loaded into scan chains before the actual capture phase begins. Configuration registers are programmed with test values in advance, allowing the capture logic to immediately begin accumulating results without sequential delays during the measurement phase
Data Source
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AI summary
Testing clock division circuitry includes generating pseudo random test pattern bits for scan chain logic in programmable clock division logic circuitry and divided clock counter circuitry. A shift clock is used to shift the test pattern bits into the scan chain logic. A capture clock signal is used in the programmable clock division logic during a non-test mode of operation. The shift clock is used to provide output shift bits from the scan chain logic to a multi-input shift register (MISR). Once all the output shift bits for the test pattern bits are provided to the MISR, a final test signature from the MISR is compared to an expected test signature to determine whether the programmable clock division logic circuitry and divided clock counter circuitry are free of faults.