BIST Clock Control via Bit Sequence Mapping
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Solution Overview
Problem
Logic Built In Self-Test (BIST) architectures face inefficiencies due to the need for multiple intervals to test designs with multiple asynchronous clocks and resets, leading to increased test time and memory requirements, as well as dependencies between interacting clock domains that impact test coverage.
Innovation Solution
A method and system that generate a sequence of bits, map them to combinations, and use an enable signal to control asynchronous signals in a single interval, allowing for simultaneous pulsing of groupable and ungroupable clocks without creating dependencies between clock domains, thereby reducing test time and memory needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple intervals are used to pulse each asynchronous clock and reset separately, then interactions between asynchronous domains are avoided, but test time and test data storage requirements increase
Solution Approach 1:
The patent merges multiple asynchronous clock domains into a single test interval by using a master clock to synchronize the pulsing of multiple clocks and resets. Instead of dedicating separate intervals to each asynchronous signal, the invention combines them into one coordinated interval where all necessary clocks and resets are pulsed simultaneously under master clock control, thereby reducing test time while maintaining test validity.
Solution Approach 2:
The patent introduces dynamic control mechanisms where a controller selectively enables or disables specific clock domains based on their interaction relationships. This dynamic approach allows the system to adaptively manage multiple asynchronous clocks within a single interval by activating only those domains that can operate together without causing harmful interactions, optimizing both test time and reliability.
2Reliability
If multiple intervals are used to pulse each asynchronous clock and reset separately, then interactions between asynchronous domains are avoided, but on-chip memory requirements increase
Solution Approach 1:
The patent merges multiple asynchronous clock domains into a single test interval by using a master clock to synchronize the pulsing of multiple clocks and resets. Instead of dedicating separate intervals to each asynchronous signal, the invention combines them into one coordinated interval where all necessary clocks and resets are pulsed simultaneously under master clock control, thereby reducing test time while maintaining test validity.
Solution Approach 2:
The patent creates a universal test interval structure that can accommodate multiple different clock and reset combinations within a single interval. The controller is designed to universally manage various asynchronous domain configurations, allowing one interval to serve multiple testing purposes rather than requiring separate dedicated intervals for each clock domain, thus reducing memory requirements.
3Productivity
If a single interval is used to pulse multiple asynchronous clocks simultaneously, then test time and memory requirements are reduced, but interactions between asynchronous domains may occur
Solution Approach 1:
The patent introduces a master clock as an intermediary that mediates between multiple asynchronous clock domains. The master clock coordinates and synchronizes the pulsing of subordinate clocks, ensuring that they operate in a controlled manner within a single interval. This intermediary mechanism allows simultaneous operation of multiple clocks while preventing harmful interactions through centralized control.
Solution Approach 2:
The patent implements feedback control where the controller monitors the state of multiple clock domains and dynamically adjusts their activation based on detected interactions. When potential harmful interactions are detected, the controller selectively disables affected clock domains, providing real-time feedback control that maintains test validity while maximizing the use of single-interval testing.
Data Source
AI summary
A method for testing a design is provided. The method includes generating a sequence of bits, mapping the sequence of bits to a combination, and generating an enable signal based on the combination. The enable signal enables an asynchronous signal in the design. The method also includes driving an element of the design based on the enabled asynchronous signal.