Self-test Output for High-density BIST Using External Comparators
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Solution Overview
Problem
Conventional BIST methods for high-density VLSI circuits face challenges such as complex timing closure, silicon area reduction, and extensive timing verification, especially in large embedded memory arrays, which complicates the testing of wide-word width memories and increases design cycle times.
Innovation Solution
A self-test output system for high-density BIST, which includes a BIST controller coupled with comparators and output registers, performs write operations, receives PASS/FAIL signals, and generates diagnostic data, allowing for serial data logging and uninterrupted testing of embedded memories until a failure is detected, using flip-flops, XOR gates, and OR gates to manage data comparison and output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BIST methods are used for high-density VLSI circuits, then memory testing can be performed, but timing closure becomes difficult and design cycle times increase
Solution Approach 1:
The comparator function is extracted from the BIST controller and implemented as a separate external module. This separation allows the BIST controller to focus on test sequence generation and control, while the comparator independently handles data comparison, eliminating timing constraints that would otherwise require extensive verification of the integrated controller design.
Solution Approach 2:
The patent introduces an external comparator as an intermediary component between the memory array and the BIST controller. This mediator handles the complex comparison operation externally, simplifying the BIST controller's timing requirements and reducing the overall design verification burden while maintaining full testing capability.
2Reliability
If conventional BIST methods are used for high-density VLSI circuits, then memory testing can be performed, but silicon area for BIST increases
Solution Approach 1:
The comparator logic is extracted from the BIST controller block and implemented as external logic. This reduces the silicon area occupied by the BIST controller itself, as the comparison function is distributed to external resources, thereby lowering the on-chip BIST overhead while preserving full testing functionality.
Solution Approach 2:
The external comparator can serve multiple purposes: it compares actual memory outputs with expected values during BIST operations, and can potentially be reused for other comparison functions in the design. This multi-functionality reduces the need for dedicated comparison logic within the BIST controller, minimizing silicon area usage.
3Reliability
If wide-word width memories are tested using conventional BIST, then complete test coverage can be achieved, but complex read architecture and multiplexers are required
Solution Approach 1:
The comparison function is extracted from the complex read architecture, allowing the memory read paths to remain simple and dedicated. The external comparator handles the complexity of comparing wide-word outputs with expected values, eliminating the need for complex on-chip multiplexing and comparison logic while achieving complete test coverage.
Solution Approach 2:
Instead of integrating the comparator within the BIST controller and complexity-prone read architecture, the patent inverts the approach by placing the comparator externally. This reversal simplifies the internal memory read architecture to basic output paths, while the external comparator handles all comparison complexity, reducing overall device complexity.
Data Source
AI summary
A method, apparatus and system of a self-test output for high density BIST are disclosed. In one embodiment, an integrated circuit includes one or more memories, a BIST controller coupled to the one or more memories to perform write operation and to receive a PASS/FAIL signal from each embedded memory and one or more comparators coupled to the one or more memories latch mutually identical outputted data coming from the memories upon a rising edge of an ORDY signal. In addition, the comparators may compare the latched mutually identical outputted data and output associated PASS/FAIL signal to the BIST controller. The BIST controller registers the received PASS/FAIL result upon receiving the PASS/FAIL signal from the comparators. The integrated circuit may include output registers coupled to the BIST controller and the comparators output a data log substantially serially upon receiving a SHIFT/CLK signal from the BIST controller.