BIST Diagnostic Collector for Logic Devices

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Solution Overview

Problem

Conventional built-in self-test systems (BIST) for logic devices fail to provide diagnostic information about fault-indicating responses in a timely manner, preventing the identification of faulty components during testing, which is crucial for process optimization and control in production.

Innovation Solution

A diagnostic information collector is integrated into the logic device, which temporarily stores responses from scan chains and generates a representative signature after each output shift operation, allowing for immediate identification of fault-indicating responses and enabling the ATE to suspend normal testing operations to receive diagnostic information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If response compression is used in BIST to reduce data flow, then data transmission efficiency is improved, but diagnostic information about faulty components is lost

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoiddiagnostic information
Core Design Contradiction:
Loss of energyVSLoss of information

Solution Approach 1:

The patent segments the monolithic digital signature into multiple representative signatures, each corresponding to a specific scan chain or logic block. This segmentation allows the ATE to identify which specific component failed while maintaining data compression benefits. The digital signature generator is divided into multiple subsystems, each generating a representative signature for its associated scan chain.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent adds a new dimension to the compression process by generating representative signatures at multiple hierarchical levels - both individual scan chain level and aggregate level. This multi-dimensional approach preserves diagnostic information about specific faulty components while maintaining overall data compression efficiency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If digital signature generation is performed after complete test sequence, then test coverage is improved, but fault identification timing is delayed

Engineering Contradiction:
Improvetest coverageVSAvoidfault identification timing
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary generation of representative signatures during the test sequence execution itself, rather than waiting for completion. Each scan chain generates its representative signature as tests are being applied, enabling early fault identification. The ATE can suspend normal operations and request diagnostic information immediately upon detecting a failed representative signature.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements continuous feedback by comparing representative signatures against expected values during test execution. When a mismatch is detected, the system provides immediate feedback about the faulty component, allowing real-time fault identification and potential test suspension without waiting for complete test sequence execution.

Inventive Principle:
Principle #23Feedback

3Ease of operation

If BIST provides only pass/fail result, then test simplicity is improved, but process optimization capability is reduced

Engineering Contradiction:
Improvetest simplicityVSAvoidprocess optimization capability
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent makes the test system universal by enabling it to serve multiple functions: simple pass/fail determination for quick screening, and detailed diagnostic information generation for process optimization. The same representative signature generation mechanism supports both simple operation modes and detailed analysis modes, making the system adaptable to different production needs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7797599B2Diagnostic information capture from logic devices with built-in self test
Publication Date: 2010.09.14 ADVANTEST CORP
  • US7797599B2 patent drawing
  • US7797599B2 patent drawing
  • US7797599B2 patent drawing

AI summary

From a logic device comprising logic circuits and a built-in self-test system (BIST) comprising scan chains, diagnostic information is obtained by using the scan chains to apply a stimulus vector to the logic circuits, to capture responses of the logic circuits to the stimulus vector and to shift the captured responses towards the outputs of the scan chains; generating a representative signature representing the responses output by the scan chains; concurrently storing the responses output by the scan chains temporarily such no more than a most-recently output subset of the responses is stored; determining whether the representative signature is a fault-indicating representative signature; and, when the representative signature is a fault-indicating representative signature, outputting at least some of the stored responses. The output responses are usable as diagnostic information. The most-recently output subset of the responses is composed of fewer than all of the responses generated in response to the stimulus vector.