Built-In Self-Test Circuitry for Dynamic Clock Frequency Testing
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Solution Overview
Problem
Conventional circuit testing methods allocate a fixed amount of test time for each clock speed, leading to significant overhead time, especially for faster clock speeds, resulting in inefficient use of time during testing integrated circuits at multiple frequencies.
Innovation Solution
Integrated circuits with built-in self-test circuitry and clock synthesizer capabilities that generate test clocks at various frequencies, allowing on-chip clock generation and reducing wait times by dynamically adjusting test clock frequencies based on test results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed amount of test time is allocated for each test iteration regardless of clock speed, then testing can be performed at multiple clock speeds, but significant overhead time is wasted especially at faster clock speeds
Solution Approach 1:
The patent implements dynamic test time allocation where the test time for each iteration is adjusted based on the clock speed being tested. Faster clock speeds receive proportionally less test time while slower clock speeds receive more time, eliminating the waste of allocating fixed time to all iterations regardless of their actual testing requirements.
Solution Approach 2:
The system changes the test time parameter dynamically based on the clock speed parameter. By linking test time allocation to the actual clock frequency being tested, the system optimizes the testing process by providing appropriate time resources for each test condition without wasting time on iterations that complete quickly.
2Measurement precision
If test iterations are performed at faster clock speeds, then more accurate test results can be obtained, but the fixed test time allocation causes nonnegligible overhead time
Solution Approach 1:
The patent applies dynamic time allocation that adapts to each test iteration's clock speed. Faster clock speed iterations that provide more accurate results are allocated appropriate time without the overhead waste caused by fixed time allocation, allowing precise testing to proceed efficiently.
3Device complexity
If conventional fixed test time allocation is used, then testing procedure is simple, but overall test run time is increased due to overhead
Solution Approach 1:
The patent implements a dynamic test time allocation system that adjusts test time based on clock speed. While this adds some complexity to the test management system, it dramatically improves productivity by eliminating the overhead time waste that occurs with fixed time allocation, especially at faster clock speeds.
Data Source
AI summary
An integrated circuit may have a circuit under test. The integrated circuit may have a clock generation circuit that receives a reference clock from a tester and that generates a corresponding core clock. The integrated circuit may have a built in self test circuit and a clock synthesizer that receives the core clock. The built in self test circuit may provide clock synthesizer control signals that direct the clock synthesizer to produce test clock signals at various test clock frequencies. The test clock at the test clock frequencies may be applied to the circuit under test during circuit testing. The circuit under test may assert a pass signal when the circuit tests are completed successfully. The built in self test circuit may inform the tester of the maximum clock frequency at which the circuit under test successfully passes testing.