BIST Circuit Dynamic Power Measurement via Activity Customization
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Solution Overview
Problem
Conventional power measurement tools for chips are prone to errors due to logic placement and metal routing variations, fail to account for dynamic power, and do not allow for customization based on memory activity factors, leading to inaccurate power predictions and coordination challenges with customers.
Innovation Solution
A built-in-self-test (BIST) circuit that runs a customized BIST pattern in loop mode on memory, measuring dynamic power by inputting activity factors such as read, write, and search operations, and calculating power based on measured current, enabling per-memory instance activity customization and accurate power optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional power measurement tools are used, then power measurements can be obtained, but measurements are prone to error due to logic placement and metal routing variations
Solution Approach 1:
The patent introduces an intermediary measurement approach by using current probes to measure supply current directly at the memory device level, bypassing the inaccuracies introduced by logic placement and metal routing variations in conventional tools. This intermediary measurement point provides a more reliable basis for calculating dynamic power.
Solution Approach 2:
The patent replaces conventional electrical field-based power measurement tools with a method based on direct current measurement and mathematical calculation. By measuring supply current and multiplying by supply voltage, the system substitutes complex electrical field measurements with simpler, more reliable current measurements.
2Use of energy by moving object
If typical power measurement tools are used, then power measurements can be obtained, but dynamic power is not accounted for even though it takes up the majority of total power in modern chips
Solution Approach 1:
The patent segments power measurement into distinct components by separately measuring and calculating dynamic power (Pdynamic = Vsupply × Isupply) and leakage power (Pleakage = Vsupply × Ileakage). This segmentation allows dynamic power, which constitutes the majority of total power in modern chips, to be accurately captured and reported independently.
Solution Approach 2:
The patent implements dynamic power measurement by capturing supply current during active BIST operations and during idle states, then calculating the difference to determine dynamic power consumption. This dynamic measurement approach tracks real-time power changes during different operational states.
3Reliability
If more test patterns are run to improve BIST quality, then BIST quality improves, but total test time increases to many millions of cycles
Solution Approach 1:
The patent applies partial action by running a representative subset of BIST test patterns rather than all possible patterns. By selecting patterns that adequately exercise the memory device for power measurement purposes, the system achieves sufficient BIST quality without the excessive test time required for complete pattern coverage.
Solution Approach 2:
The patent performs preliminary power measurements during BIST operations to establish baseline dynamic and leakage power values. These preliminary measurements enable early termination of excessive testing when sufficient data is collected, avoiding unnecessary millions of cycles while maintaining measurement accuracy.
4Adaptability or versatility
If conventional power measurement tools are used, then power measurements can be obtained, but they do not allow for customization based on memory activity factors
Solution Approach 1:
The patent implements dynamic customization by allowing users to configure BIST patterns and activity factors according to specific application requirements. The system can be adapted to measure power under different memory access patterns, workloads, and operational conditions, providing versatile and application-specific power characterization.
Solution Approach 2:
The patent enables parameter customization by allowing modification of BIST test patterns, activity factors, and measurement conditions to match specific customer applications. This parameter flexibility ensures that power measurements accurately reflect real-world usage scenarios, improving prediction accuracy for different chip designs and applications.
Data Source
AI summary
The present disclosure relates to a device including a built-in-self-test (BIST) circuit configured to run a BIST pattern in a loop mode on a memory which is customized for activity factors corresponding to a programmable number of operations, the BIST circuit being further configured to measure dynamic power on a supply while running the BIST pattern in the loop mode on the memory.