Memory BIST Error Detection with ECC Awareness
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Solution Overview
Problem
Existing built-in self-test (BIST) circuits for memory systems do not effectively utilize error correction capabilities, leading to unnecessary fault reporting and potential system failures by detecting correctable errors as faults, which can result in unnecessary repairs or replacements.
Innovation Solution
Incorporating an error corrector circuit that generates and uses error correction codes to identify and correct data errors within the memory wrapper, allowing the BIST circuit to ignore correctable faults and focus on uncorrectable errors, thereby generating a more accurate error report.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If typical BIST memory circuitry is configured to write pseudo random data to the memory and read the same pseudo random data back to detect faults, then fault detection capability is improved, but false positive fault reporting increases due to inability to distinguish correctable errors from uncorrectable faults
Solution Approach 1:
The patent introduces an intermediary component (error correction code circuit or status flag) that mediates between the memory array and BIST circuitry. This intermediary provides error correction capability and distinguishes between correctable and uncorrectable errors, allowing the BIST to accurately identify only uncorrectable faults without false positives from correctable errors.
Solution Approach 2:
The patent implements feedback mechanisms where error correction status information is fed back to the BIST circuitry. The BIST reads error correction status flags or uses error correction code circuits to determine whether detected errors are correctable or uncorrectable, enabling accurate fault identification by filtering out correctable errors from the fault report.
2Reliability
If BIST circuitry detects all errors including correctable ones, then comprehensive error detection is achieved, but unnecessary repairs or replacements are triggered due to false positives
Solution Approach 1:
The error correction code circuit or status flag acts as an intermediary that filters error information before it reaches the BIST fault detection logic. This intermediary distinguishes between correctable and uncorrectable errors, allowing comprehensive error detection while preventing false positive fault reports that would trigger unnecessary repairs.
Solution Approach 2:
The patent applies local quality by treating different types of errors differently within the same memory system. Correctable errors are handled locally by the error correction code circuit and filtered out from fault reports, while uncorrectable errors are propagated to the BIST for fault reporting. This selective handling prevents unnecessary repairs for correctable errors.
3Measurement precision
If error correction codes are incorporated into the memory wrapper, then ability to differentiate correctable and uncorrectable errors is improved, but device complexity increases
Solution Approach 1:
The error correction code circuit serves multiple functions: it corrects errors in normal operation, provides error detection capability, and enables the BIST to distinguish between correctable and uncorrectable errors. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity while improving error classification accuracy.
Solution Approach 2:
The memory system performs self-service through the error correction code circuit that automatically corrects errors without external intervention. The BIST leverages this self-service capability by reading error correction status flags to determine fault status, reducing the need for additional complex testing infrastructure.
Data Source
AI summary
Technologies for built-in self-testing of a memory array using error detection and correction code knowledge include identifying data errors between pseudo random data written to the memory array and the data read back from the memory array and ignoring those data errors determined to be correctable. The data errors may be determined to be correctable if an error corrector circuit can correct those errors or if the number of errors per memory chuck is less than a number of errors correctable by the error correct circuit.