Built-in Self-Test Circuit for High-Speed I/O Port Testing
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Solution Overview
Problem
Conventional testers are unable to perform high-speed tests on integrated circuits with GHz-level I/O ports due to their limited operating speed, typically around 100 MHz, which is insufficient for detecting defects in high-performance integrated circuits.
Innovation Solution
A built-in self-test (BIST) circuit is introduced in the memory controller, comprising a detecting unit, flag unit, and selecting unit, which generates a stable logic signal at the I/O port, allowing a low-speed tester to detect test results by utilizing a reset signal, serial output signal, and serial enable signal to set and clear a flag signal, indicating the functionality of the I/O port.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional tester is used to test high-speed I/O ports, then the tester structure remains simple and operating cost is low, but the tester cannot detect defects in high-performance integrated circuits due to speed limitations
Solution Approach 1:
A BIST circuit is introduced as an intermediary component between the high-speed I/O port and the low-speed tester. The BIST circuit includes a detecting unit that captures high-speed signal relationships, a flag unit that processes detection results, and a selecting unit that outputs test results at speeds compatible with conventional testers. This mediator enables low-speed testers to accurately test high-speed interfaces without requiring tester speed upgrades.
Solution Approach 2:
The BIST circuit creates a simplified copy of the high-speed signal relationship at a lower speed. The detecting unit captures the relationship between serial output signals and enable signals, and the selecting unit reproduces this test result information at a speed that conventional testers can handle, allowing accurate testing without matching the original high-speed characteristics.
2Productivity
If the I/O port operates at GHz level speed, then the data transmission capability is improved, but the tester operating speed becomes insufficient to detect defects
Solution Approach 1:
The detecting unit performs preliminary detection of the high-speed signal relationship before the low-speed tester arrives. It captures whether the serial output signal and enable signal maintain their expected relationship during the high-speed operation, storing this result in the flag unit. This preliminary action allows the slow tester to simply read the pre-captured result without needing to operate at high speed.
Solution Approach 2:
The BIST circuit operates periodically: the detecting unit monitors the high-speed signals during active transmission periods, processes the detection results during intermediate periods, and outputs test results during tester-access periods. This periodic operation allows the system to handle both high-speed data transmission and low-speed testing without conflict.
Data Source
AI summary
A built-in self-test circuit (BIST) applied to a high speed I/O port is provided. The BIST circuit includes a detecting unit, a flag unit and a selecting unit. The detecting unit has a first input terminal for receiving a serial output signal, a second input terminal for receiving a serial enable signal, and an output terminal for generating a detection signal. The flag unit receives the detection signal and generates a flag signal. The selecting unit receives the serial output signal, the serial enable signal and the flag signal. When a reset signal is at a first level, the selecting unit transmits the serial output signal and the serial enable signal to the I/O port. When the reset signal is at a second level, the serial output signal and the serial enable signal possesses a predetermined relationship.