BIST Circuit Isolation for High-Speed Wafer Testing
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Solution Overview
Problem
The existing methods for performing built-in self tests (BIST) on semiconductor memory devices during the wafer level process are limited by load effects generated from external automatic test equipment, restricting execution speed and application range.
Innovation Solution
A semiconductor memory device with a BIST circuit connected to a separate test pad, allowing it to generate and apply test pattern data independently, thereby avoiding load effects on the data input/output pads and enabling high-speed testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BIST is performed by connecting external ATE directly to data input/output pad, then testing can be performed, but execution speed and application range are limited due to load effect
Solution Approach 1:
The patent divides the testing interface into two separate parts: a test pad for connecting to ATE during wafer-level testing, and data input/output pads for normal operation. This segmentation allows the BIST circuit to receive test signals through the test pad without the load effects that would occur if ATE were connected directly to the data input/output pads, thereby maintaining both testing capability and execution speed
Solution Approach 2:
The test pad acts as an intermediary interface between the external ATE and the BIST circuit. By introducing this intermediate connection point, the patent enables test signals to be transmitted to the BIST circuit without subjecting the data input/output circuitry to harmful load effects, thus preserving both the ability to perform comprehensive tests and maintaining high execution speed
2Reliability
If BIST is performed by connecting external ATE directly to data input/output pad, then testing can be performed, but application range is limited due to load effect
Solution Approach 1:
By separating the test interface from the data input/output interface, the patent enables the BIST circuit to perform a wider variety of tests including those that would be impossible or problematic with direct ATE connection to data pads. This segmentation expands the application range while maintaining testing capability
Solution Approach 2:
The test pad serves as an intermediary that enables diverse testing applications by isolating the BIST circuit from the constraints of the data input/output interface. This allows the system to accommodate various test scenarios and configurations without being limited by the electrical characteristics of the data pads
3Productivity
If separate test pad is used for BIST, then load effects are avoided and high-speed testing is enabled, but device complexity increases
Solution Approach 1:
The test pad is designed to serve multiple functions: it enables high-speed BIST operations by avoiding load effects, and can be integrated into existing wafer-level testing infrastructure. By making this single interface element multi-functional, the patent achieves high execution speed without proportionally increasing overall device complexity
Solution Approach 2:
The BIST circuit is designed to be self-sufficient by including an internal pattern generation unit that can generate test patterns independently. This self-service capability reduces the complexity of external testing equipment requirements while maintaining high execution speed through autonomous operation
Data Source
AI summary
A semiconductor memory device included in each of a plurality of chips which are divided by a scribe lane and formed on an upper surface of a wafer, includes a memory core and a built-in self test (BIST) circuit. The memory core includes a memory cell array that stores data and a data input/output circuit connected to a data input/output pad. The BIST circuit is connected to a test pad that is separate from the data input/output pad. The BIST circuit generates test pattern data including first parallel bits based on commands and addresses received from an external automatic test equipment (ATE) during a wafer level test process performed on the semiconductor memory device. The BIST circuit tests the memory core by applying the test pattern data to the memory cell array through the data input/output circuit.