BIST Judgment Circuit for Accurate ECC Error Correction Assessment
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Solution Overview
Problem
Existing BIST circuits in semiconductor devices cannot accurately determine whether error correction by the ECC circuit is possible, leading to unnecessary system failure notifications even when errors can be corrected, which affects system reliability and boot time.
Innovation Solution
A BIST circuit with an address generation circuit, test data generation circuit, and judgment circuit that compares read data with expected values to determine if the number of error bits is within the error correction range, allowing for accurate assessment of error correction possibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional BIST circuit is used to diagnose memory errors, then error detection capability is provided, but false failure notifications occur when errors can be corrected by ECC circuit
Solution Approach 1:
The judgment circuit is segmented into multiple functional units: an error detection unit that identifies memory errors, an error counting unit that counts the number of erroneous bits, and a correction capability judgment unit that compares the counted errors against ECC correction thresholds. This segmentation enables precise determination of whether errors are correctable, preventing false failure notifications while maintaining reliable error detection.
2Measurement precision
If BIST circuit performs comprehensive error checking, then error detection precision is improved, but boot time increases due to thorough diagnosis
Solution Approach 1:
The BIST circuit performs partial error checking by counting the number of erroneous bits and comparing against ECC correction thresholds. Rather than exhaustively analyzing every possible error scenario, the circuit performs sufficient checking to determine whether errors fall within correctable ranges, achieving adequate precision while reducing boot time through optimized diagnostic depth.
3Device complexity
If BIST circuit cannot discriminate error correction possibility, then device complexity is reduced, but system reliability deteriorates due to unnecessary failure notifications
Solution Approach 1:
The judgment circuit acts as an intermediary between the error detection function and the failure notification system. It receives error information from the memory diagnosis, counts the erroneous bits, compares them against ECC correction capabilities, and only triggers failure notifications when errors exceed correctable thresholds. This intermediary function adds minimal complexity while significantly improving system reliability by filtering out false notifications.
Data Source
AI summary
An address generation circuit generates a target address to be tested in a memory. A test data generation circuit generates write data for the address and expected value data for read data from the address. A judgment circuit compares matching/non-matching of the read data and the expected value data, for each address, judges that error correction is possible when the number of non-matching bits is within a range of numbers of bits to be error-corrected by an ECC circuit, and judges that error correction is not possible when the number is not within the range.