BIST Circuit for Memory Defect Detection
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Solution Overview
Problem
The inefficiency of testing internal memory devices in system-on-chip (SoC) technology due to limited channels and high-speed test limitations in dedicated equipment, necessitating a more effective method for defect detection in semiconductor manufacturing.
Innovation Solution
Incorporating a Built-In Self Test (BIST) circuit within the memory device that compares test pattern data with sensing data to generate a comparison signal, marking failures, and selectively latching column addresses with latch enable signals to identify and output fail column addresses during a test operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dedicated test equipment is used for testing internal memory devices in SoC, then measurement precision can be achieved, but productivity decreases due to limited channels and high-speed test limitations
Solution Approach 1:
The memory device performs self-testing through integrated BIST circuits that generate test patterns, execute tests internally, and detect defects without external dedicated test equipment. The test pattern generation circuit creates test data, the memory block stores it, and the test data output circuit retrieves and compares results to identify fail column addresses, enabling the system to test itself autonomously.
Solution Approach 2:
The testing function is merged with the memory device itself by integrating BIST circuits, test pattern generation logic, and comparison circuits within the same chip. This combines the memory functionality with self-diagnostic capabilities, eliminating the need for separate dedicated test equipment and enabling simultaneous operation of multiple test channels.
2Reliability
If all column addresses are output during test operation, then complete test coverage is achieved, but loss of information increases due to mixing of pass and fail addresses
Solution Approach 1:
The output data is segmented into two distinct parts: column addresses and fail indicator signals. Each column address is paired with its corresponding fail indicator, allowing the system to process complete test coverage while clearly distinguishing between pass and fail addresses. This segmentation prevents mixing of results and maintains accurate failure identification.
Solution Approach 2:
A fail indicator signal acts as an intermediary between the test comparison result and the output data. This intermediary marks fail column addresses by setting specific bits in the output signal, enabling the system to transmit both all column addresses for complete coverage while simultaneously identifying which addresses represent failures without confusion.
Data Source
AI summary
The present disclosure relates to a memory device including a BIST circuit and an operating method thereof. The memory device includes a comparison circuit comparing test pattern data with sensing data to generate a comparison signal, a status information generating circuit generating a fail mask signal by marking data in which a failure occurs in the sensing data in response to the comparison signal, a column address generating circuit generating column addresses sequentially increasing in response to an input/output strobe signal, a latch enable signal generating circuit generating a latch enable signal in response to the fail mask signal, and an input/output circuit receiving the column addresses and selectively latching a column address in which a failure occurs among the column addresses in response to the latch enable signal.