BIST Memory Grouping for Peak Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor integrated circuits face issues with memory grouping methods that lead to increased retries and peak power due to simultaneous switching during memory tests, as existing methods do not effectively manage memory test cycles and power consumption.
Innovation Solution
The proposed solution involves dividing memories into blocks based on test cycles and grouping them by memory type and clock frequency, using BIST control circuits to manage and sequence memory tests, and employing clock phase control and counter control circuits to distribute memory access and reduce simultaneous switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single BIST control circuit controls many memories in layout-based memory grouping, then device complexity is reduced, but peak power consumption increases due to simultaneous switching
Solution Approach 1:
The patent divides memories into multiple groups based on test cycles and memory types, with each group having its own BIST control circuit. This segmentation prevents all memories from being tested simultaneously, thereby reducing peak power consumption while maintaining manageable device complexity through systematic organization
Solution Approach 2:
The patent implements periodic testing by controlling different memory groups at different time intervals based on their test cycle requirements. Memories are tested in staggered periods rather than simultaneously, which reduces instantaneous power consumption while ensuring all memories are thoroughly tested
2Productivity
If memories are grouped by memory type or test cycle information, then test organization is improved, but wiring congestion increases
Solution Approach 1:
The patent applies layout-based grouping where memories of the same type are placed in specific local regions of the chip. This local organization reduces wiring congestion by minimizing the distance and complexity of interconnects between memories of the same type, while still maintaining effective test organization through the grouped structure
3Device complexity
If memory tests are executed without considering test cycle differences, then device complexity is reduced, but the number of retries increases
Solution Approach 1:
The patent changes the test control approach by incorporating test cycle parameters into the grouping strategy. Memories are grouped based on their specific test cycle requirements, allowing the system to adapt the testing sequence and timing to match each memory's characteristics, thereby improving test success rate without excessive complexity
Data Source
AI summary
According to a certain embodiment, the semiconductor integrated circuit includes a plurality of memories and a first control circuit configured to control the plurality of memories. The first control circuit includes a first state transition circuit configured to execute at least one of write control and read control during an operation of the plurality of memories; and a second state transition circuit connected to the first state transition circuit, the second state transition circuit capable of causing the first state transition circuit to sequentially execute tests of the plurality of memories.