BIST Circuit Memory Initialization Using PRNG Patterns

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Solution Overview

Problem

Existing methods for testing and initializing memory circuitry in electronic devices are complex, costly, and often require external testing equipment, which can be inefficient and prone to long test times, especially after the devices are deployed in the field.

Innovation Solution

Incorporating a Built-In Self-Test (BIST) circuit within the memory circuitry that can operate in both self-test and memory initialization modes, using a PRNG circuit to generate pseudo-random sequences for initializing memory during power-on-reset events and normal operation, ensuring different random content for each device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If external testing equipment is used to test memory circuitry, then testing can be performed, but the system complexity increases, cost increases, and test time increases

Engineering Contradiction:
Improvememory testing capabilityVSAvoidtesting system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the memory initialization function and self-test capability into a single integrated circuit block, eliminating the need for separate external testing equipment. The BIST circuit is merged with the memory interface, allowing both initialization and testing to be performed by the same hardware component that would normally be used for memory operations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory system performs its own initialization and testing through the built-in self-test circuit, which can autonomously generate test patterns and evaluate memory functionality without requiring external testing equipment. The system serves its own testing needs internally.

Inventive Principle:
Principle #25Self-service

2Reliability

If external testing equipment is used to initialize memory, then memory can be initialized, but the test time becomes long and the process becomes inefficient

Engineering Contradiction:
Improvememory initializationVSAvoidinitialization test time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The BIST circuit is designed to perform memory initialization as a preliminary action before normal operation begins. The circuit generates initialization patterns and performs the initialization process automatically when the system powers up or enters test mode, eliminating the need for time-consuming external testing procedures.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If BIST circuit is used for self-test, then testing can be performed without external equipment, but the circuit is generally only used for self-tests and not for memory initialization

Engineering Contradiction:
Improvetesting system simplificationVSAvoidBIST circuit functionality
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The BIST circuit is designed to perform multiple functions: it can generate pseudo-random patterns for initialization, perform standard BIST operations for self-testing, and interface with memory in various modes. This multi-functional design allows the same circuit to serve both initialization and testing purposes, increasing its versatility while maintaining the benefit of not requiring external equipment.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9595350B2Hardware-based memory initialization
Publication Date: 2017.03.14 NXP USA INC
  • US9595350B2 patent drawing
  • US9595350B2 patent drawing
  • US9595350B2 patent drawing

AI summary

Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state.