BIST Parity Control Circuit for Single-Pass Memory Module Testing
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Solution Overview
Problem
Existing memory module testing methods require multiple iterations to accurately determine the reliability of memory cells, leading to increased testing time without ensuring reliability.
Innovation Solution
The implementation of a BIST logic circuit with a parity control circuit that generates substituted parity data, allowing for a single test operation to cover all memory cells without altering parity data positions, thereby improving testing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple test iterations are performed to ensure memory cell reliability, then testing accuracy is improved, but testing time increases
Solution Approach 1:
The patent applies preliminary action by generating substituted parity data in advance through the parity control circuit before the actual memory testing begins. The parity control circuit pre-processes the main data to create substituted parity data that covers all memory cells, eliminating the need for multiple iterative tests. This preliminary preparation enables single-pass testing while maintaining comprehensive coverage and accuracy.
2Productivity
If substituted parity data is generated to cover all memory cells in a single test, then testing efficiency is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the parity control circuit to perform multiple functions: generating substituted parity data, controlling the substitution process, and ensuring comprehensive memory cell coverage. This multi-functional approach consolidates what would otherwise require separate testing components and iterations, achieving high testing efficiency without proportionally increasing device complexity.
3Reliability
If parity data positions are altered to improve test coverage, then testing completeness is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by transforming the parity data from its original form into substituted parity data with different characteristics. The parity control circuit modifies the parity data parameters (such as bit patterns and positions) to create substituted versions that provide comprehensive coverage of all memory cells. This parameter transformation achieves complete test coverage while managing complexity through systematic data transformation rather than complex hardware reconfiguration.
Data Source
AI summary
A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.