Built-in Self-Test Circuit for Row Hammering Detection
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Solution Overview
Problem
Row hammering vulnerabilities in memory chips can lead to data disturbances and unauthorized access, posing significant security and reliability concerns, especially as technology scales down and memory density increases.
Innovation Solution
A built-in self-test (BIST) circuit is integrated into the chip to detect rows vulnerable to row hammering by writing initial values to a row, reading adjacent rows multiple times, and comparing the original and final values to identify any bit flips, thereby designating vulnerable rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory density is increased through technology scaling, then storage capacity is improved, but row hammering vulnerabilities increase causing data disturbances
Solution Approach 1:
The BIST circuit performs preliminary testing during chip manufacturing to identify rows vulnerable to row hammering before the chip is deployed. By conducting this test in advance, vulnerable rows are detected and marked, allowing the system to prevent future attacks by avoiding these rows during normal operation.
Solution Approach 2:
The memory chip performs self-diagnosis through the integrated BIST circuit that automatically tests for row hammering vulnerabilities without external testing equipment. The circuit autonomously writes test patterns, reads adjacent rows multiple times, detects bit flips, and identifies vulnerable rows, enabling the chip to characterize its own security properties.
2Measurement precision
If adjacent rows are read multiple times to detect row hammering, then vulnerability detection capability is improved, but test time and energy consumption increase
Solution Approach 1:
The BIST circuit applies excessive action by reading adjacent rows many more times than normally required for standard memory operations. This excessive reading amplifies the row hammering effect on vulnerable rows, making bit flips more likely to occur during the test and improving detection accuracy.
Solution Approach 2:
The test methodology changes key parameters including writing complementary patterns (0x55 and 0xAA) to adjacent rows and performing multiple read cycles. By varying the test patterns and read counts, the system optimizes the probability of detecting vulnerable rows while managing test duration.
3Reliability
If a BIST circuit is integrated into the chip to test for row hammering, then security is improved, but device complexity increases
Solution Approach 1:
The BIST circuit functionality is merged with the existing memory controller and test infrastructure of the chip. By integrating the row hammering test capabilities into the existing memory interface and control logic, the patent avoids adding completely separate testing hardware, thereby reducing the overall complexity increase.
Solution Approach 2:
The BIST circuit is designed to perform multiple functions: it can test for row hammering vulnerabilities, characterize memory behavior, and provide diagnostic information. This multi-functionality justifies the added complexity by delivering comprehensive security and reliability benefits from a single integrated circuit block.
Data Source
AI summary
A method for testing a chip includes writing, by a built-in self-test (BIST) circuit of the chip, a first row of a memory of the chip with a first set of values and reading, by the BIST circuit, a second row of the memory a first plurality of times. The second row is adjacent to the first row. The method also includes reading, by the BIST circuit, the first row to extract a second set of values from the first row and based on determining that at least one of the second set of values differs from a corresponding one of the first set of values, designating the first row as a vulnerable row.