Control Chip BIST Circuit Test Vector Storage Optimization
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Solution Overview
Problem
The existing test methods for control chips face challenges due to limited memory space in automatic test equipment (ATE) for storing test vectors, leading to longer test times and higher costs, and a high dependence on ATE, which increases costs and reduces test efficiency.
Innovation Solution
A built-in self-test (BIST) circuit in the control chip is used to read and store test vectors in a target memory chip, allowing for efficient testing by reducing the reliance on ATE and utilizing additional memory space for vector storage, enabling all test vectors to be loaded once and processed quickly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If ATE is used to store test vectors in its internal memory, then test vectors can be stored and executed, but the limited memory space of ATE requires multiple loading operations which increases test time and reduces test efficiency
Solution Approach 1:
The patent merges the ATE's internal memory with the DUT's internal memory to form a unified test vector storage system. The ATE stores a first portion of test vectors in its internal memory while the DUT stores a second portion in its internal memory, eliminating the need for multiple loading operations and enabling all test vectors to be loaded simultaneously for efficient testing.
Solution Approach 2:
The patent transitions from a single-dimension storage approach (ATE internal memory only) to a multi-dimension storage architecture by utilizing both ATE and DUT internal memories as separate storage dimensions. This dimensional expansion allows the system to overcome the memory capacity limitations of the ATE alone.
2Reliability
If ATE is directly used to test the control chip, then testing can be performed, but the high dependence on ATE increases test costs and reduces test efficiency
Solution Approach 1:
The patent enables the DUT to perform self-testing by utilizing its own internal memory to store and execute test vectors. The control chip's internal memory serves as both the storage medium and execution environment, reducing dependence on external ATE equipment while maintaining test accuracy through the built-in self-test capability.
Solution Approach 2:
The patent extracts the test vector storage and execution function from the ATE and relocates it to the DUT's internal memory. This extraction reduces the operational dependence on ATE equipment while preserving the essential testing functionality through the DUT's autonomous test execution capability.
3Productivity
If a large number of DA pads are used on the control chip to increase test capacity, then more test vectors can be processed, but the costs of probe cards increase and peripheral pins are limited
Solution Approach 1:
The patent utilizes the DUT's internal memory as a virtual expansion of the ATE's memory capacity. Instead of physically adding more DA pads and probe card connections, the system creates a logical memory expansion by storing test vectors in the DUT's internal memory, thereby increasing test throughput without increasing physical connectivity complexity.
Data Source
AI summary
Embodiments of the present disclosure provide a test method and apparatus for a control chip, and an electronic device, which relate to the field of semiconductor device test technologies. The control chip includes a built-in self-test BIST circuit. The method is performed by the BIST circuit. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.