Bistable Memory Cell Topology for Low-Power Data Retention
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Solution Overview
Problem
Current memory circuits, such as VNR-SRAMs and NV-SRAMs, face challenges in miniaturization due to the large number of transistors required, which increases cell area and power consumption, and there is a need for faster neural network processing with reduced power consumption.
Innovation Solution
A bistable circuit configuration using a specific arrangement of FETs with different conductivity types and control circuits to reduce the number of transistors and optimize voltage settings for low power consumption and improved noise margin, allowing for miniaturization and efficient neural network processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory circuits (VNR-SRAM, NV-SRAM) are used, then data retention and reliability are improved, but the number of transistors increases and cell area expands
Solution Approach 1:
The patent merges the functions of multiple transistors into a simplified bistable circuit configuration. By using a specific arrangement of transistors with different conductivity types (PMOS and NMOS) and combining their functions, the circuit achieves data retention capability with fewer transistors than conventional VNR-SRAM or NV-SRAM cells, thus reducing cell area while maintaining reliability
Solution Approach 2:
The bistable circuit is designed to perform multiple functions: data storage, data retention, and integration with neural network processing. The same circuit structure serves as both the memory element and the processing element, eliminating the need for separate dedicated memory circuits and reducing overall transistor count
2Reliability
If conventional memory circuits with more transistors are used, then data retention is improved, but power consumption increases
Solution Approach 1:
By merging the functions of multiple transistors into a compact bistable circuit, the patent reduces the total number of active elements that consume power. The simplified circuit structure with fewer transistors inherently consumes less power while maintaining data retention capability through the clever arrangement of PMOS and NMOS transistors in feedback configurations
Solution Approach 2:
The patent utilizes parameter changes in transistor conductivity types (switching between PMOS and NMOS) to achieve data retention with lower power consumption. By strategically assigning different conductivity types to different transistor positions in the bistable circuit, the design optimizes the balance between retention reliability and power consumption
3Productivity
If existing neural network processing methods are used, then processing speed is improved, but power consumption and transistor count remain high
Solution Approach 1:
The bistable circuit is designed to serve dual purposes: as a memory element for storing neural network weights and as a processing element for performing computations. This multi-functionality allows the same circuit to both store data and process it, eliminating the need for separate high-power processing circuits and achieving fast neural network processing with reduced power consumption
Solution Approach 2:
The patent segments the neural network processing function into distributed bistable circuit elements, where each circuit performs local computations on stored weights. This segmentation allows parallel processing across multiple circuits, achieving high processing speed while each individual circuit consumes minimal power due to its simplified structure
Data Source
AI summary
A bistable circuit includes a pair of inverter circuits each including a first FET being connected between a power supply line and an intermediate node and having a gate coupled to an input node and a first conductivity type channel, a second FET being connected between the intermediate node and an output node and having a gate coupled to the input node and the first conductivity type channel, a third FET being connected between the intermediate node and a bias node, a fourth FET being connected between the output node and a control line and having a gate coupled to a word line and a second conductivity type channel, wherein the pair of inverter circuits are connected in a loop shape, and gates of the third FETs of the pair of inverter circuits are coupled to one of the input and output nodes of the pair of inverter circuits.