Bistable Memory Circuit With Fewer Transistors for Data Retention
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Solution Overview
Problem
Existing memory circuits, such as VNR-SRAMs and NV-SRAMs, face challenges in miniaturization due to the large number of transistors required, leading to increased cell area and power consumption, especially when processing neural networks.
Innovation Solution
A bistable circuit configuration is proposed, which includes a first and second inverter circuit, each comprising specific FET configurations, along with memory nodes and control lines, to reduce the number of transistors and enhance miniaturization while maintaining data retention and processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory circuits (VNR-SRAMs, NV-SRAMs) are used, then data retention and processing functionality are achieved, but the number of transistors increases leading to larger cell area and higher power consumption
Solution Approach 1:
The patent merges the functions of multiple transistors into a simplified bistable circuit configuration. By using cross-coupled inverters with shared control signals and optimized transistor arrangements, the circuit achieves data retention functionality with fewer transistors compared to conventional VNR-SRAM and NV-SRAM designs, directly resolving the contradiction between reliability and device complexity
Solution Approach 2:
The bistable circuit is designed to perform multiple functions (data storage, retention, and processing) using a unified transistor configuration. The same circuit structure serves as both the storage element and the processing unit for neural network operations, reducing the overall transistor count while maintaining data retention capability
2Area of stationary object
If the number of transistors is reduced for miniaturization, then cell area decreases, but power consumption may increase due to reduced noise margin and weaker signal stability
Solution Approach 1:
The patent optimizes the electrical parameters of the reduced transistor circuit, including threshold voltages, channel widths, and lengths of the transistors, to achieve the right balance between area and power consumption. By carefully adjusting these parameters, the circuit maintains adequate noise margins while operating at lower power levels compared to conventional designs with larger transistor counts
Solution Approach 2:
The circuit employs dynamic voltage scaling and mode switching capabilities, allowing it to adapt its power consumption characteristics based on operational requirements. The bistable circuit can switch between different operating modes (e.g., retention mode and read/write mode) with optimized power characteristics for each mode, ensuring efficient power usage despite the reduced transistor count
3Productivity
If conventional SRAM configurations are used for neural network processing, then processing functionality is achieved, but power consumption increases due to continuous refresh requirements and large transistor count
Solution Approach 1:
The patent extracts and eliminates the continuous refresh mechanism from conventional SRAM designs. By using a bistable circuit configuration that inherently maintains its state without periodic refreshing, the design removes the energy-consuming refresh operations while preserving fast processing capabilities for neural network computations
Solution Approach 2:
The bistable circuit is designed to maintain its own state autonomously without external refresh signals. The cross-coupled inverter structure provides self-latching functionality where the circuit's own output signals reinforce its stored state, eliminating the need for external power-intensive refresh operations and enabling low-power neural network processing
Data Source
AI summary
A bistable circuit includes a pair of inverter circuits each including a first FET being connected between a power supply line and an intermediate node and having a gate coupled to an input node and a first conductivity type channel, a second FET being connected between the intermediate node and an output node and having a gate coupled to the input node and the first conductivity type channel, a third FET being connected between the intermediate node and a bias node, a fourth FET being connected between the output node and a control line and having a gate coupled to a word line and a second conductivity type channel, wherein the pair of inverter circuits are connected in a loop shape, and gates of the third FETs of the pair of inverter circuits are coupled to one of the input and output nodes of the pair of inverter circuits.