Bistable Memory Cell Retention Using a Third Low Supply Voltage
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Solution Overview
Problem
Existing nonvolatile retention SRAMs face limitations in reducing energy consumption during power gating due to leakage current and mode switching latency, while store-free operations in NV-SRAMs are less effective as memory capacity increases, leading to increased power consumption and latency.
Innovation Solution
An electronic circuit with a cell array of bistable circuits that includes first and second inverter circuits with switchable modes, where unnecessary memory cells are powered off and switched to a lower power mode, and a control circuit manages power supply voltages to optimize energy retention and reduce unnecessary operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If ULV retention is performed on all memory cells during power gating, then standby power is reduced without losing memory content, but leakage current and mode switching energy overhead increase the break-even time
Solution Approach 1:
The patent applies local quality by differentiating the treatment of memory cells based on data importance. Important data in critical memory cells retain ULV retention capability while non-critical cells are allowed to enter deeper low-power states. This selective approach reduces overall leakage current without requiring mode switching for all cells, thereby reducing break-even time while maintaining standby power benefits.
Solution Approach 2:
The memory array is segmented into multiple blocks with different power management characteristics. Some blocks are configured for ULV retention while others can be fully powered down. This segmentation allows the system to optimize power consumption on a block-by-block basis, reducing the number of cells requiring mode switching and thereby reducing overall break-even time.
2Loss of energy
If mode switching is performed for all cells during power gating, then power consumption is reduced, but mode switching latency and energy overhead increase break-even time
Solution Approach 1:
The patent extracts the mode switching operation from being a universal requirement and applies it only to specific memory cells that contain important data. By taking out the mode switching requirement from the general case and applying it selectively, the patent reduces the total number of mode switching operations, thereby reducing cumulative latency and energy overhead while maintaining power consumption benefits.
3Reliability
If store operation is performed on all memory cells, then data is retained after power gating, but power consumption due to leakage current in blocks waiting for store operation increases
Solution Approach 1:
The patent applies local quality by differentiating between memory cells containing important data and those containing non-critical data. Cells with important data undergo store operations to ensure data retention, while cells with non-critical data are allowed to enter deeper low-power states without store operations. This selective approach maintains reliability for critical data while reducing overall power consumption during the store operation phase.
Data Source
AI summary
An electronic circuit includes a cell array including memory cells each including a bistable circuit that includes first and second inverter circuits, each having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in the transfer characteristics, and being switchable between the first and second modes, and a control circuit configured to, after powering off a first memory cell that store data that are not required to be retained, put the bistable circuit in a remaining second memory cell into the second mode, and supply a second power supply voltage that allows the bistable circuit in the second mode to retain data and is lower than a first power supply voltage supplied to the bistable circuit when data is read and/or written, to the bistable circuit in the second memory cell while maintaining the second mode.