Bistable Overcurrent Logic for Power Transistor Short-Circuit Protection
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Solution Overview
Problem
Existing overcurrent detection methods for power transistors, particularly those based on wide bandgap materials, are inefficient and prone to causing damage due to rapid current rise during short circuits, and often require additional complex circuitry increasing costs and complexity.
Innovation Solution
A bistable overcurrent detection logic is implemented, which transitions to a stable overcurrent state when an overcurrent condition is detected, remaining in this state until a specific signal resets it, thus preventing immediate reactivation of the power transistor and avoiding potential damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional overcurrent detection methods are used, then the power transistor can be protected from damage, but additional complex circuitry is required which increases costs and device complexity
Solution Approach 1:
The overcurrent detection functionality is merged with the existing gate driver circuit by sharing the status output terminal OC. The detection logic is integrated within the gate driver chip, eliminating the need for separate external detection circuits and reducing overall device complexity while maintaining protection capability
Solution Approach 2:
The status output terminal OC serves multiple functions: it indicates the switching state of the power transistor during normal operation and simultaneously serves as an overcurrent detection output. This multi-functionality reduces the need for additional dedicated detection circuits and pins
2Reliability
If sense transistors are used for overcurrent detection, then detection can be implemented on-chip, but the protection may be released too quickly allowing the transistor to resume operation with excessive current
Solution Approach 1:
The latch circuit is pre-configured with feedback connections that automatically maintain the overcurrent detection state. When overcurrent is detected, the latch sets the status output terminal OC to indicate overcurrent, and the feedback mechanism ensures this state persists even after the current returns to normal, preventing premature reactivation
Solution Approach 2:
The latch circuit incorporates feedback paths where the output state influences the input conditions. The status output terminal OC feeds back to the detection logic, ensuring that once overcurrent is detected, the protection state is maintained until explicitly reset, preventing the transistor from resuming operation with excessive current
3Reliability
If solid state circuit breakers or slope monitoring are implemented, then overcurrent protection can be achieved, but additional external circuitry and pins are required increasing costs and complexity
Solution Approach 1:
The overcurrent detection logic is merged with the gate driver circuitry on the same chip. The detection logic shares the status output terminal OC with the gate driver, eliminating the need for separate external detection circuits and reducing the number of required pins
Solution Approach 2:
The gate driver circuit performs self-diagnosis by monitoring its own output state through the status terminal OC. The detection logic is integrated within the driver chip, allowing the circuit to monitor itself without requiring external monitoring equipment or additional complex external circuitry
Data Source
Figure 1~2
Figure 3A~3B
Figure 3C~4
AI summary
A device is provided comprising a power transistor and an overcurrent detection logic. The overcurrent detection logic has a first stable state providing a first signal level on a status output terminal and a second stable state providing a second signal level on the status output terminal. The overcurrent detection logic changes from the first stable state to the second stable state in response to detecting that a current through the power transistor exceeds a current limit. The overcurrent detection logic remains in the second state when the current through the transistor drops below the limit after exceeding the current limit.