Bi-stable SRAM Bit Cells Using III-V Compounds for High-Speed Operation
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Solution Overview
Problem
Conventional one transistor (1T) NMOS bi-stable SRAM bit cells have a relatively slow write speed due to their design limitations, despite consuming less area compared to conventional 6T SRAM bit cells.
Innovation Solution
The development of bi-stable SRAM bit cells formed from III-V compounds, which include a substrate and well layers doped with specific materials, forming field-effect transistors and bipolar junction transistors, allowing for higher electron mobility and faster operating speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional 1T NMOS bi-stable SRAM bit cell design is used, then area consumption is reduced, but write speed becomes slow
Solution Approach 1:
The patent changes the material parameter from conventional silicon-based NMOS to III-V compound semiconductors, which have fundamentally different electrical characteristics including higher electron mobility. This material parameter change enables both compact area and high-speed operation by leveraging the superior carrier transport properties of III-V materials
Solution Approach 2:
The invention employs composite material structures combining III-V compound semiconductors with specific doping configurations to create a unified device that achieves both small area and high speed. The composite nature of III-V materials with tailored doping profiles enables simultaneous optimization of area and write speed that cannot be achieved with single-material conventional approaches
2Speed
If III-V compounds are used to increase electron mobility, then operating speed is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the SRAM bit cell into distinct functional regions with specific doping types (n-type source/drain regions, p-type floating well, n-type buried well) within the III-V material structure. This segmentation allows each region to be optimized for its specific function while maintaining overall manufacturability through systematic material growth and processing techniques
Solution Approach 2:
The invention applies local quality by creating spatially varying doping concentrations and types within the III-V material structure. Different regions have tailored doping profiles (n-type, p-type, and undoped areas) to optimize local electrical properties for specific functions such as carrier injection, storage, and transport, thereby achieving high operating speed while maintaining manufacturing feasibility through localized material modification
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of III-V compounds in bi-stable SRAM bit cells enhances operating speeds by leveraging higher electron mobility, outperforming conventional SRAM bit cells with lower electron mobility materials.
Implementation Method 1
The III-V compounds used in the bi-stable SRAM bit cell have a higher electron mobility than materials employed in conventional complementary metal-oxide semiconductor (CMOS) technology
Implementation Method 2
an ionization electron-hole pair is generated at a PN junction corresponding to the buried N-well (i.e., N) and the floating P-well (i.e., P) as a result of capacitive coupling, such that hole carriers flow into the floating P-well (120) through the collectors C1, C2
Implementation Method 3
Employing the elements above also results in two (2) bipolar junction transistors (BJTs) formed within the bi-stable SRAM bit cell. Based on the formation of the BJTs, a charge can be stored in the second well layer, wherein the charge corresponds to a data value of the bi-stable SRAM bit cell
Data Source
AI summary
Bi-stable static random access memory (SRAM) bit cells formed from III-V compounds and configured to achieve higher operating speeds are disclosed. In one aspect, a bi-stable SRAM bit cell includes substrate, first well layer formed over substrate from a III-V compound doped with a first type material, and second well layer formed over first well layer from a III-V compound doped with a second type material. Channel layer is formed over second well layer from a III-V compound doped with the first type material. Source and drain regions are formed over channel layer from a III-V compound doped with the first type material, and gate region is formed over channel layer. Bipolar junction transistors (BJTs) are formed such that a data value can be stored in second well layer. Collector tap electrode is configured to provide access to collector of each BJT for reading or writing data.