Bit-Adjacency Switched CDAC for Low-Distortion Conversion
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Solution Overview
Problem
Serial charge-redistribution cyclic digital-to-analog converters (CDACs) suffer from distortion due to capacitor mismatch errors and charge injection errors, with existing solutions either arbitrarily swapping capacitor configurations or performing cumulative swap decisions that slow down conversion and increase complexity.
Innovation Solution
A CDAC design that selectively connects first and second capacitors in two configurations based on adjacent bits of the input word, using a decision rule to determine capacitor roles for each bit and swapping capacitors only when necessary, thereby reducing distortion and simplifying the architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If capacitor configurations are swapped based on cumulative calculation from MSB to LSB, then distortion is reduced, but conversion speed decreases and complexity increases
Solution Approach 1:
The patent inverts the conventional MSB-to-LSB processing order by implementing LSB-to-MSB conversion. This inversion allows the most significant bit decisions to be made last, enabling faster convergence and reducing the number of iterative calculations needed, thereby improving conversion speed while maintaining distortion reduction through selective capacitor swapping
Solution Approach 2:
The patent performs preliminary actions by pre-determining capacitor configuration decisions based on LSB adjacency patterns before full conversion completes. The controller examines adjacent LSB values and pre-configures capacitor connections, reducing the computational burden during active conversion and improving overall conversion speed
2Manufacturing precision
If capacitor configurations are swapped based on cumulative calculation, then distortion is reduced, but device complexity increases
Solution Approach 1:
The patent applies local quality by implementing capacitor swapping only when adjacent bit values indicate a need for correction, rather than uniformly swapping for all bits. The controller examines specific adjacent bit pairs and selectively configures capacitors based on local bit patterns, reducing overall system complexity while maintaining distortion reduction where needed
Solution Approach 2:
The patent segments the conversion process into independent bit-processing stages that can operate in parallel or sequential fashion. By dividing the N-bit conversion into smaller computational units that process adjacent bit pairs independently, the patent reduces the complexity of cumulative calculations while maintaining accuracy through localized capacitor configuration decisions
3Device complexity
If arbitrary capacitor configuration is used, then architecture is simplified, but distortion increases
Solution Approach 1:
The patent dynamically changes capacitor configuration parameters based on input bit patterns. The controller monitors adjacent bit values and adjusts capacitor connections in real-time, transitioning between different configuration states to minimize distortion. This parameter adaptation maintains architectural simplicity while achieving low distortion through data-driven configuration selection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) errors, improves conversion speed, and simplifies the CDAC architecture, achieving about 13.4% improvement in RMS INL and 99.6% improvement in RMS DNL errors compared to traditional methods.
Implementation Method 1
Charge redistribution in CDAC 700 is achieved by selective control of MOS-type switches SB0-SB3 and SBINIT
Data Source
AI summary
A cyclic digital to analog converter (CDAC) includes: first and second capacitors C1 and C2; an arrangement of switches selectively controllable to connect C1 and C2 in one of at least two charging-and-sharing configurations, the first configuration having the first capacitor C1 as a charging capacitor CCH and the second capacitor C2 as a sharing capacitor CSH, namely CCH=C1 and CSH=C2, and the second configuration having CCH=C2 and CSH=C1; and a controller to toggle the arrangement of switches between the first and second configurations based upon adjacent bits of a given input word.