Bit Arrangement in Multi-Level Modulation for Balanced Error Tolerance
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Solution Overview
Problem
In the HSDPA system, there is a disparity in error tolerance among data blocks due to variations in phase and amplitude during radio transmission, leading to differences in reception quality and inefficient error correction, with blocks having higher or lower tolerance capabilities, resulting in potential errors exceeding correction capabilities or unnecessary re-transmissions.
Innovation Solution
A transmitting apparatus is developed that generates bit sequences for both data blocks to align with signal points on a phase plane, preferentially arranging systematic bits in positions more prone to errors, using a bit sequence generating unit to equalize the occupation rate of predetermined bits, thereby enhancing error correction efficiency and reducing re-transmission of unnecessary signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data blocks are transmitted using conventional bit arrangement methods, then transmission speed is maintained, but error tolerance varies significantly among blocks due to phase and amplitude variations during radio transmission
Solution Approach 1:
The patent applies local quality by differentiating bit positions based on their error susceptibility. Specifically, it identifies that certain bit positions (e.g., lower bits in 16-QAM) are more prone to errors than others, and accordingly arranges systematic bits preferentially in less error-prone positions while placing other bits in more vulnerable positions. This localized differentiation of bit arrangement strategies equalizes error tolerance across multiple data blocks, resolving the inconsistency in reception quality.
2Reliability
If systematic bits are arranged in error-prone positions, then error correction capability is improved, but transmission efficiency decreases due to increased re-transmissions
Solution Approach 1:
The patent changes the parameter of bit arrangement strategy by introducing a systematic bit arrangement method that considers both error susceptibility and block-level variations. Instead of uniformly arranging bits across all blocks, it dynamically adjusts which bits are placed in error-prone positions based on the specific characteristics of each data block. This parameter change optimizes the balance between error correction capability and transmission efficiency, reducing unnecessary re-transmissions.
3Device complexity
If uniform bit arrangement is used across all data blocks, then implementation complexity is reduced, but reception quality varies due to different error tolerance in each block
Solution Approach 1:
The patent implements local quality by introducing targeted variations in bit arrangement for different data blocks. Rather than using a completely uniform arrangement, it applies specific arrangement rules that account for local characteristics of each block, such as the number of systematic bits and their positions. This localized approach maintains reasonable implementation complexity while significantly improving reception quality consistency across blocks.
Data Source
AI summary
A transmitting apparatus comprising circuitry operable to generate a plurality of bit sequences using bits included in a first data block and a second data block, circuitry operable to control the plurality of bit sequences to correspond to a signal point on the phase plane, comprising a bit sequence generating unit operable to control the generation of the bit sequences to adjust an occupation rate occupied with predetermined bits included in the first data block to be closer to an occupation rate occupied with predetermined bits included in the second data block in regard to bit positions of the predetermined bits, based on an error tolerance of the respective bit sequences generated resulting from the correspondence to a signal point on the phase plane, and circuitry operable to transmit the signals obtained by multi-level modulations in accordance with each signal point.