Bit Block Stream Parity Checking for M/N Switching BER Detection
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Solution Overview
Problem
Current bit error detection methods in communications technologies, such as CRC and BIP, face challenges in accurately measuring bit error rates, especially when there are few user service packets, and result in low bearer efficiency due to the occupation of fixed frame bytes, making them difficult to implement in M/N bit block switching scenarios with high implementation complexity.
Innovation Solution
A bit block stream bit error detection method that involves sending boundary bit blocks and calculating parity check results using flexible algorithms like xBIP-y and flexBIP-z, allowing for dynamic configuration of detection parameters and efficient use of bandwidth, enabling accurate error detection on both end-to-end and non-end-to-end paths with minimal impact on user service.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If packet-based CRC detection is used, then error detection capability is improved, but bearer efficiency deteriorates due to fixed frame byte occupation
Solution Approach 1:
The patent segments the bit block stream into N individual bit blocks, each independently processed for error detection. Instead of applying CRC to entire packets, the invention applies lighter-weight parity check bytes to smaller bit block units, reducing the overhead ratio while maintaining detection capability across the stream.
Solution Approach 2:
The patent changes the detection parameter from fixed CRC-32 (32-bit check) to configurable parity check byte lengths (1-8 bits). This allows optimization of the detection strength versus overhead trade-off, enabling lighter detection mechanisms that consume fewer frame bytes while still providing adequate error detection for the bit block stream.
2Reliability
If BIP check is performed on each block, then error detection is achieved, but bearer efficiency deteriorates due to high overhead
Solution Approach 1:
The patent applies partial error detection by using parity check bytes that cover only portions of the bit block stream rather than comprehensive checking of every block. The configurable parity length (1-8 bits) allows selective application of detection strength, providing adequate error detection while minimizing overhead to preserve bearer efficiency.
3Ease of manufacture
If fixed frame structure is used for error detection, then implementation is simplified, but adaptability deteriorates
Solution Approach 1:
The patent introduces dynamic configurability to the error detection mechanism, allowing the parity check byte length (1-8 bits) and the number of bit blocks per detection unit (N) to be adjusted based on service requirements. This dynamic parameter configuration enables the system to adapt between lightweight detection for high-efficiency scenarios and stronger detection for reliability-critical applications.
Solution Approach 2:
The patent enables flexible parameter configuration including parity check byte length (1-8 bits), number of bit blocks N, and detection positioning (end-to-end or non-end-to-end). These changeable parameters allow the system to adapt to different service types, bandwidth requirements, and reliability needs without being constrained by a fixed frame structure.
4Reliability
If packet-based detection is used, then error detection works with user packets, but measurement accuracy deteriorates when user packets are scarce
Solution Approach 1:
The patent establishes continuous error detection capability by applying parity checks to the bit block stream itself, independent of user packet presence. The detection mechanism operates continuously on the transport stream, allowing accurate BER measurement even when user service packets are absent or scarce, because the detection is decoupled from user data and applied to the carrier structure.
Data Source
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AI summary
Disclosed are a bit block stream bit error detection method and device, to resolve problems of relatively high implementation difficulty and relatively low carrying efficiency of a bit error detection method in an M/N bit block switching scenario. The method includes: sending a first boundary bit block, where the first boundary bit block is used to distinguish N bit blocks to be subsequently sent; sequentially sending an Ith bit block, where I is an integer greater than or equal to 1 and less than or equal to N; determining a first parity check result and a second parity check result, where a check object of the first parity check result includes m consecutive bits of each bit block in the N bit blocks, a check object of the second parity check result includes n consecutive bits of each bit block in the N bit blocks, and at least one of m and n is greater than or equal to 2; and sending a second boundary bit block, the first parity check result, and the second parity check result, where the second boundary bit block is used to distinguish the N bit blocks that have been sent.