Bit Block Truncation for Low Latency Ethernet Traffic

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Solution Overview

Problem

Existing Ethernet technologies face limitations in reducing latency due to restrictions at the physical layer, where bit blocks cannot be truncated, hindering the achievement of low latency and high reliability required for emerging services like 5G mobile bearers and industrial Internet applications.

Innovation Solution

A bit block processing method is introduced where a tag bit block with a length field is added, allowing bit block segments to be truncated into multiple segments during forwarding, with each segment containing a tag bit block and related data bit blocks, enabling flexible preemption and prioritization of critical traffic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If Ethernet frame preemption technology is used to decrease latency of critical traffic, then latency is reduced, but the decrease is limited due to restriction by shortest packet in Ethernet

Engineering Contradiction:
ImprovelatencyVSAvoidflexibility in latency reduction
Core Design Contradiction:
Loss of timeVSAdaptability or versatility

Solution Approach 1:

The patent segments the Ethernet frame into multiple bit block segments at the physical layer, where each segment can be independently transmitted. This segmentation allows critical traffic to be preempted at any bit block boundary rather than being constrained by minimum packet length requirements, thereby achieving more flexible and greater latency reduction while maintaining Ethernet compatibility.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If bit block truncation is implemented at physical layer, then flexibility in traffic prioritization is improved, but bit block cannot be truncated in traditional Ethernet physical layer

Engineering Contradiction:
Improveflexibility in traffic prioritizationVSAvoidimplementation complexity
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent introduces a tag bit block as an intermediary element that carries length field information and segment identification. This tag enables the physical layer to track and truncate bit blocks at appropriate boundaries without complex processing, simplifying the implementation of flexible traffic prioritization while maintaining protocol compatibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the parameter representation by introducing a length field in the tag bit block that specifies the number of data bit blocks. This parameter change allows dynamic control of bit block segment lengths and enables flexible truncation points without requiring complex physical layer modifications, thus improving ease of implementation.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If tag bit block with length field is added to enable bit block segment truncation, then latency and reliability are improved, but device complexity increases

Engineering Contradiction:
Improvereliability of critical traffic transmissionVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary action by adding the tag bit block with length field information at the beginning of data transmission. This pre-tagging approach allows receiving devices to know in advance the segment structure and boundaries, enabling simple truncation and reassembly operations without complex real-time processing, thus improving reliability while minimizing added complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3694125B1Bit block processing method, and node
Publication Date: 2023.12.20 HUAWEI TECH CO LTD
  • EP3694125B1 patent drawingFigure 1
  • EP3694125B1 patent drawingFigure 2A
  • EP3694125B1 patent drawingFigure 2B

AI summary

Embodiments of the present invention provide a bit block processing method, including: sequentially receiving a first tag bit block and N data bit blocks through a first port, where the first tag bit block includes a first length field; sequentially sending the first tag bit block and M data bit blocks in the N data bit blocks through a second port; and sequentially sending a second tag bit block and L data bit blocks in remaining N-M data bit blocks of the N data bit blocks through the second port, where the second tag bit block includes a second length field, a value of the first length field is greater than a value of the second length field by M, and M, N, and L are all integers greater than or equal to 0. According to the method provided in the embodiments of the present invention, a tag bit block and data bit blocks following the tag bit block form a bit block segment. During forwarding of the bit block segment, the bit block segment is truncated into at least two bit block segments, and each truncated bit block segment includes one tag bit block.