Multiplying Bit-Cell Reset Control for Low-Energy In-Memory Computing
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Solution Overview
Problem
Existing in-memory computing technologies face challenges in reducing energy consumption and improving speed for matrix-vector multiplication operations, particularly in neural networks, due to limitations in data movement and quantization noise in large-scale integrations.
Innovation Solution
The implementation of a fully row/column-parallel in-memory computing structure using capacitor-based mixed-signal computation, where input signal presentation is controlled to reduce power consumption during charging and discharging of capacitors, employing a hybrid analog/digital scheme with bit-parallel/bit-serial operations and dynamic switch selection criteria.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional in-memory computing structures are used for matrix-vector multiplication, then computational operations can be performed within memory bit-cells, but energy consumption increases due to charging and discharging of summing capacitors during reset and evaluation modes
Solution Approach 1:
The patent implements dynamic switch selection criteria that adaptively control the switching behavior during reset and evaluation modes. The switches dynamically select between different capacitor coupling configurations based on the operational phase, optimizing energy consumption while maintaining computational functionality. This dynamic control allows the system to reduce unnecessary charging/discharging operations while preserving the core matrix-vector multiplication capability.
Solution Approach 2:
The patent changes the voltage/charge levels applied to summing capacitors based on the operational mode. During reset mode, capacitors are discharged to a first voltage level, while during evaluation mode, they are charged to a second voltage level. This parameter change approach allows the system to minimize energy consumption by only charging capacitors when necessary for computation, rather than continuously maintaining charge levels.
2Use of energy by moving object
If data movement is reduced in large-scale matrix-vector multiplications, then power consumption decreases, but computational speed may be affected
Solution Approach 1:
The patent segments the computational process into distinct reset and evaluation modes, with each mode optimized for specific operations. The reset mode prepares capacitors by discharging them, while the evaluation mode performs the actual multiplication and accumulation. This segmentation allows data to remain in memory during the reset phase, reducing data movement overhead while maintaining computational speed during the evaluation phase.
Solution Approach 2:
The patent performs preliminary capacitor discharge operations during the reset mode before the actual computation in evaluation mode. By preparing the capacitors in advance (clearing them to a known state), the system reduces the computational burden during the actual multiplication phase, allowing faster computation without requiring excessive data movement during the critical evaluation stage.
3Adaptability or versatility
If capacitor-based mixed-signal computation is implemented, then in-memory computing functionality is achieved, but complexity of controlling input signal presentation increases
Solution Approach 1:
The patent designs the switch network to perform multiple functions: selecting between different capacitor banks, controlling charge/discharge paths, and enabling different computational modes (reset and evaluation). This multi-functional switch design reduces the overall number of control signals needed compared to having dedicated switches for each function, thereby reducing control complexity while maintaining versatile in-memory computing functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in energy-efficient, high-speed computing by minimizing power consumption and enhancing computational efficiency in matrix-vector multiplications, while maintaining signal-to-quantization noise ratio, thus addressing the limitations of previous technologies.
Implementation Method 1
charge-domain in-memory computing... compute operations within memory bit-cells provide their results as charge, typically using voltage-to-charge conversion via a capacitor
Implementation Method 2
a plurality of switches configured during a reset mode of operation to selectively couple capacitor input terminals to respective first voltages, and during an evaluation mode of operation to selectively couple capacitor input terminals to respective second voltages
Data Source
AI summary
Various embodiments comprise systems, methods, architectures, mechanisms, apparatus, and improvements thereof for in-memory computing using charge-domain circuit operation to provide energy efficient, high speed, capacitor-based in-memory computing. Various embodiments contemplate controlling input signal presentation within in-memory computing structures/macros in accordance with predefined or dynamic switch selection criteria to reduce energy consumption associated with charging and/or discharging summing capacitors during reset and evaluation operating modes of multiplying bit-cells (M-BCs).