Bit Cell Internal Voltage Control for SRAM Data Retention
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Solution Overview
Problem
In memory devices like SRAM, lowering the internal voltage level for a write operation can lead to data retention failures in unselected bit cells if maintained for too long, as it reduces the voltage potential across these cells.
Innovation Solution
A system comprising a pulse generator and a voltage detector is used to lower the internal voltage level during a write operation, with the voltage detector sending a reset signal to the pulse generator when the voltage drops past a reset trigger level, ensuring the internal voltage is restored to its original level before data retention issues occur, utilizing RC delay data to manage timing delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the internal voltage level is lowered for a write operation, then the write operation can be performed more easily, but data retention in unselected bit cells deteriorates
Solution Approach 1:
The patent applies dynamics by making the internal voltage level adjustable rather than fixed. The voltage level is dynamically lowered during write operations and then restored to its original level, allowing the system to adapt its electrical characteristics based on operational requirements while maintaining data integrity in unselected cells.
Solution Approach 2:
The patent implements periodic action through the cyclic lowering and restoring of the internal voltage level. The voltage is temporarily reduced for the duration of the write operation and then periodically restored to its original level, creating a controlled temporal pattern that enables write operations without compromising data retention.
2Productivity
If the internal voltage level is lowered for too long, then data retention failure occurs in unselected bit cells
Solution Approach 1:
The patent applies preliminary action by proactively restoring the internal voltage level to its original level as soon as the write operation completes or when a predetermined time threshold is approached. This preventive restoration ensures that unselected bit cells never experience prolonged voltage reduction that would cause data retention failure.
Solution Approach 2:
The patent implements feedback mechanisms to monitor the duration of voltage lowering and trigger restoration when appropriate. The system uses timing information and operational status feedback to determine when to restore the voltage level, ensuring that the voltage remains lowered only for the necessary duration to complete the write operation.
Data Source
AI summary
Among other things, techniques for facilitating a write operation to a bit cell are provided. A pulse generator initializes lowering of an internal voltage level associated with a bit cell that is to be written to by a write operation. In this way, the bit cell is placed into a writeable voltage state, such that a potential of the bit cell can be overcome by the write operation. A voltage detector sends a reset signal to the pulse generator based upon the pulse generator lowering the internal voltage level past a reset trigger level. Responsive to receiving the reset signal, the pulse generator initializes charging of the internal voltage level to an original voltage level. In this way, the lowering of the internal voltage level is controlled so that one or more other bit cells are not affected (e.g., suffer data retention failure) by the relatively lower internal voltage level.