Bit Cell Write-Assist Voltage Equalization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing memory systems face slowed write response times due to contention between write circuitry and retention circuitry, especially at lower operating voltages, which reduces the frequency of write operations.
Innovation Solution
The implementation of an equalization system and retention strength control system, which includes an equalizer and retention strength circuitry, respectively, to reduce contention by equalizing voltage differences and controlling retention strength prior to write operations, allowing write operations to be performed with a voltage swing less than the operating voltage, thereby enhancing write response times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If write operations are performed at lower operating voltages, then energy consumption is reduced, but write response time is slowed due to contention between write circuitry and retention circuitry
Solution Approach 1:
The retention strength circuitry is activated before the write operation to reduce retention strength in advance. This preliminary action prevents contention during the write operation by weakening the retention circuitry's hold capability before the write signal arrives, allowing the write circuitry to operate without delay even at lower voltages.
Solution Approach 2:
The retention strength circuitry dynamically adjusts its retention strength based on operational needs. By making the retention strength variable rather than fixed, the system can optimize between energy consumption and write speed by reducing retention strength when needed for write operations while maintaining it during read operations.
2Reliability
If retention strength is increased to maintain logic states, then data retention is improved, but write operation speed is reduced due to contention
Solution Approach 1:
The retention strength circuitry is activated before the write operation to reduce retention strength in advance. This preliminary action prevents contention during the write operation by weakening the retention circuitry's hold capability before the write signal arrives, allowing the write circuitry to operate without delay even at lower voltages.
Solution Approach 2:
The retention strength circuitry dynamically adjusts its retention strength based on operational needs. By making the retention strength variable rather than fixed, the system can optimize between energy consumption and write speed by reducing retention strength when needed for write operations while maintaining it during read operations.
3Device complexity
If write circuitry operates without assistance, then device complexity is reduced, but write response time increases due to contention
Solution Approach 1:
The retention strength circuitry acts as an intermediary between the write circuitry and the storage nodes. This intermediary component mediates the contention by dynamically adjusting the retention strength to facilitate smoother write transitions, reducing the direct conflict between write and retention circuitry.
Solution Approach 2:
The retention strength circuitry is activated before the write operation to reduce retention strength in advance. This preliminary action prevents contention during the write operation by weakening the retention circuitry's hold capability before the write signal arrives, allowing the write circuitry to operate without delay even at lower voltages.
Data Source
AI summary
Methods and systems to provide bit cell write-assist, including equalization of voltages of Bit and Bit nodes of a bit cell prior to a write operation. Equalization may be performed with a pulse-controlled transistor to transfer charge between the storage nodes. Pulse width and/or amplitude may be configurable, such as to scale with voltage. Bit cell write-assist may include reduction of bit cell retention strength during equalization, which may be continued during a write operation. Write-assist may be provided to each of multiple bit cells when a write operation is directed to a subset of the bit cells, which may conserve power and/or area. A partially-decoded address may be used to provide write-assistance to multiple bit cells prior to a write operation. Write-assistance may permit writing of Bit and Bit with a voltage swing significantly lower than an operating voltage of the bit cell.