Bit Conversion Circuit for Zero-Centered Neural Network Numbers
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Solution Overview
Problem
Existing hardware implementations for centring the distribution of numbers on zero in neural networks are inefficient due to resource demands and require complex subtraction operations, which are costly in hardware terms.
Innovation Solution
A hardware module that converts bit sequences into signed integers and subsequently into floating-point numbers, utilizing bit manipulation to centre the distribution on zero without explicit subtraction, employing NOT gates and XNOR gates to determine the magnitude and sign bits, and generating a mantissa and exponent for a distribution centred on zero.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If explicit subtraction operations are used to centre the distribution of numbers on zero, then the conversion accuracy is improved, but the hardware resource demands and device complexity increase significantly
Solution Approach 1:
The patent extracts and eliminates the explicit subtraction operation from the hardware circuit. Instead of implementing a full subtractor unit, the design uses bit manipulation techniques (inversion and conditional selection) to achieve the same mathematical result of centering the distribution on zero, thereby removing the complex subtraction hardware while preserving conversion accuracy
Solution Approach 2:
The patent replaces the mechanical subtraction operation with a combination of bit inversion (logical NOT) and conditional bit selection operations. This substitution transforms a resource-intensive arithmetic operation into simpler logical operations that can be executed with fewer hardware resources while achieving the same effect of centering the number distribution
2Measurement precision
If complex subtraction operations are implemented in hardware, then the conversion precision is improved, but the operation speed and productivity decrease due to resource constraints
Solution Approach 1:
By removing the explicit subtraction operation from the hardware pipeline, the patent eliminates a resource-intensive step that would bottleneck operation speed. The bit manipulation approach uses simpler logical operations that can be executed in parallel with fewer resource constraints, thereby improving throughput while maintaining precision
Solution Approach 2:
The patent changes the operational parameters of the conversion process by replacing arithmetic subtraction with logical bit manipulation. This parameter change transforms the operation from a sequential arithmetic process to a parallel logical process, enabling faster execution without sacrificing the precision of the distribution centering
3Measurement precision
If resource-intensive subtraction operations are used, then the conversion accuracy is improved, but the ease of manufacture and implementation becomes more difficult
Solution Approach 1:
The patent extracts the subtraction operation from the implementation and replaces it with fundamental logical operations (NOT gates and conditional selection). This makes the hardware design simpler to manufacture and implement, as logical operations are more straightforward to realize in standard logic gate libraries compared to arithmetic subtraction units
Solution Approach 2:
The patent uses simple, readily available logical operations (bit inversion and conditional selection) instead of complex subtraction hardware. These logical operations can be implemented using standard, inexpensive logic gates that are universally available in digital logic libraries, making the design easier to manufacture and more cost-effective
Data Source
AI summary
A hardware module comprising circuitry configured to: store a sequence of n bits in a register of the hardware module; generate a signed integer comprising a magnitude component and a sign bit by: if the most significant bit of the sequence of n bits is equal to one: set each of the n−1 of the most significant bits of the magnitude component to be equal to the corresponding bit of the n−1 least significant bits of the sequence of n bits; and set the sign bit to be zero; if the most significant bit of the sequence of n bits is equal to zero: set each of the n−1 of the most significant bits of the magnitude component to be equal to the inverse of the corresponding bit of the n−1 least significant bits of the sequence of n bits; and set the sign bit to be one.