Bit-Decomposition Secure Computation Apparatus for RSS Communication Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current secure computation methods using (2, 3) threshold type RSS are inefficient in terms of communication amount for bit decomposition and bit combination, particularly when compared to existing methods like those described in Non-Patent Literature 2, which require a communication amount of 10n+4 bits.

Innovation Solution

A secure computation apparatus and method that employs a bit-decomposition secure computation apparatus using (2, 3) threshold type RSS with modulo 2, incorporating a full adder secure computation part to distribute and combine share values efficiently, reducing communication requirements through optimized share value storage and processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If conventional bit decomposition methods using (2, 3) threshold type RSS are used, then data confidentiality is maintained, but communication amount becomes excessively large (10n+4 bits)

Engineering Contradiction:
Improvedata confidentialityVSAvoidcommunication amount
Core Design Contradiction:
Loss of informationVSQuantity of substance

Solution Approach 1:

The patent segments the bit decomposition process into two distinct phases: (1) decomposition phase where share values are broken down into individual bits and stored in decomposed share value storage apparatus, and (2) combination phase where bits are reassembled. This segmentation allows optimization of communication protocols for each phase separately, reducing overall communication overhead while maintaining security through the (2, 3) threshold RSS structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary distribution of share values to multiple apparatuses before the actual bit decomposition and combination operations. By pre-distributing the shared secret values r1, r2, r3 to apparatuses 1, 2, and 3 respectively, the system prepares the computational state in advance, allowing subsequent bit operations to be performed with reduced communication requirements since the foundational secret sharing structure is already established.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If bit decomposition is performed for each digit using secure computation, then computation accuracy is improved, but processing time increases significantly

Engineering Contradiction:
Improvecomputation accuracyVSAvoidprocessing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent divides the multi-digit number into individual digits and performs bit decomposition on each digit separately. For each digit, the share values are decomposed into bits, processed through full adder secure computation, and then recombined. This segmented approach ensures that each digit maintains computational precision while allowing parallel processing of different digits, thereby reducing overall processing time compared to sequential full-number processing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs bit decomposition and full adder secure computation for each digit individually, which may seem excessive compared to processing the entire number as a unit. However, this partial action on each digit ensures maximum computational accuracy for each position while enabling independent optimization and parallel execution, ultimately achieving better overall efficiency and precision than monolithic processing.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If share values are distributed across multiple apparatuses for secure computation, then security is enhanced, but device complexity increases

Engineering Contradiction:
ImprovesecurityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent designs each apparatus (apparatus 1, 2, and 3) with universal functionality to perform multiple operations: storing share values, performing bit decomposition, executing full adder secure computation, and participating in bit combination. Each apparatus can independently execute the complete secure computation protocol, making the system modular and easier to manage despite the distributed architecture, thereby reducing operational complexity while maintaining security.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements a nested structure where the (2, 3) threshold RSS framework contains the bit decomposition process, which in turn contains the full adder secure computation, which finally contains the bit combination operation. This nested organization allows each layer to operate independently with well-defined interfaces, reducing system complexity by creating clear hierarchical boundaries while maintaining the security benefits of distributed computation.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS11381390B2Secure computation apparatus, system, method and program
Publication Date: 2022.07.05 NEC CORP
  • US11381390B2 patent drawing
  • US11381390B2 patent drawing
  • US11381390B2 patent drawing

AI summary

A bit-decomposition secure computation apparatus uses r1, r2, and r3 satisfying w=r1+r2+r3 mod 2{circumflex over ( )}n as share information of (2, 3) threshold type RSS (Replicated Secret Sharing) stored in a share value storage apparatus, and includes an addition sharing part that sums two values out of the share information by modulo 2{circumflex over ( )}n arithmetic and distributes the sum using (2, 3) type RSS; and a full adder secure computation part that adds the value generated by the addition sharing part by distributing the sum of the two values to share information of one remaining value other than the two values used by the addition sharing part for each digit by using secure computation of a full adder.