Bit Error Pattern Analyzer for High-Speed Data Links
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Solution Overview
Problem
Diagnosing and analyzing bit errors and bit slips in high-speed serial and parallel data links is challenging due to signal distortion and the lack of accessible measurement tools, leading to unclear root causes and time-consuming trial-and-error approaches.
Innovation Solution
A non-intrusive method using a bit error pattern tester that correlates bit errors with specific bit patterns and signal characteristics by employing a bit error rate test set augmented with an error pattern analyzer, generating pseudo-random sequences to identify correlations between error mechanisms and signal patterns, thereby determining likely causes of bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high speed Digital Sampling Oscilloscope (DSO) or other suitable analyzer tools is used to tap and analyze the signal, then measurement precision is improved, but device complexity and cost increase significantly
Solution Approach 1:
The patent uses a bit error rate test set that generates and transmits a known pseudo-random bit sequence through the data link, then compares the received sequence with the transmitted sequence to identify bit errors. This copying approach replaces the need for expensive high-bandwidth oscilloscopes by using a simpler test equipment that reproduces the test signal and compares it with the received signal to detect errors without requiring direct signal tapping or complex preprocessing.
2Measurement precision
If signal tapping is performed to analyze bit errors, then measurement precision is improved, but the signal becomes severely distorted and the measurement becomes intrusive
Solution Approach 1:
The patent employs a bit error rate test set that transmits a known pseudo-random bit sequence through the data link under test and uses the same test set to receive and analyze the transmitted signal. The test set compares the received sequence with the transmitted sequence to identify bit errors without requiring external signal tapping. This self-service approach allows the system to measure bit errors while leaving the production signal path undisturbed and avoiding the need for complex equalization or preprocessing.
3Reliability
If trial and error approach is used to tune parameters while making bit error rate measurements, then reliability is improved, but productivity decreases significantly
Solution Approach 1:
The patent uses a bit error rate test set that continuously monitors and counts bit errors in real-time as data is transmitted through the link. The test set provides immediate feedback on the bit error rate for different parameter settings, allowing technicians to quickly identify optimal configurations without performing lengthy manual measurements for each parameter combination. This automated feedback mechanism significantly reduces diagnostic time while maintaining reliable error detection.
Data Source
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AI summary
The invention relates to a method and device for testing a data link. A single-lane or multi-lane bit error tester that transmits one or more PRBS signals through the data link is augmented with a raw bit error buffer for storing bit error information for each detected error event and an error pattern analyzer. Most frequently occurring intra-lane bit error patterns, inter-lane word error patterns, and bit slip patterns are identified and their characteristics are analyzed so as to provide information indicative of root causes of the detected bit errors and bit slips.