Bit Failure Detection Circuit for Multi-Level Memory Testing
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Solution Overview
Problem
Advanced non-volatile memory devices with multi-level memory cells require efficient testing techniques to identify and disable defective memory array blocks, as existing error detection and correction circuitry struggles to handle a greater number of errors effectively.
Innovation Solution
A bit failure detection circuit that accumulates data errors by comparing read data from memory devices with reference data during a test operation, generating a flag when the sum of errors exceeds a threshold, utilizing a full adder and reference bit adder to indicate excessive errors, and including a data comparison circuit with XOR elements and a bit process addition circuit to convert M-bits into binary values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error detection and correction circuitry is used in non-volatile memory devices with multi-level memory cells, then the device can handle basic error correction, but the circuitry struggles to effectively handle a greater number of errors as memory density increases
Solution Approach 1:
The error detection and correction functionality is divided into separate specialized circuits: a bit failure detection circuit that counts total bit failures, an EDC circuit that corrects limited errors, and a monitoring circuit that tracks uncorrected errors. This segmentation allows each circuit to be optimized for its specific function, improving overall reliability without proportionally increasing complexity.
Solution Approach 2:
A bit failure detection circuit acts as an intermediary between the memory array and the EDC circuitry. It provides comprehensive bit failure counting information that enables the EDC circuit to make informed decisions about which errors to correct and which to leave uncorrected, optimizing the trade-off between correction capability and circuit complexity.
2Quantity of substance
If advanced non-volatile memory devices with multi-level memory cells are developed, then storage capacity increases, but the number of errors that occur increases making existing EDC circuitry insufficient
Solution Approach 1:
The bit failure detection circuit performs preliminary counting of all bit failures before the EDC circuit attempts correction. This preliminary action provides advance information about the error landscape, allowing the system to prepare appropriate correction strategies and monitor uncorrected errors that exceed correction capabilities.
Solution Approach 2:
The monitoring circuit provides feedback about uncorrected errors back to the system, enabling continuous tracking of error patterns. This feedback mechanism allows the system to adapt to increasing error rates associated with higher storage capacity devices and maintain reliability through informed error management decisions.
3Measurement precision
If the threshold for flag generation is set to detect all errors, then measurement precision improves, but the number of false positives increases reducing manufacturing yield
Solution Approach 1:
The system allows the error threshold for flag generation to be adjusted as a configurable parameter. This enables optimization of the threshold based on specific application requirements and memory device characteristics, balancing measurement precision with manufacturing yield by setting thresholds that account for normal variation while still detecting genuine defects.
Data Source
AI summary
A bit failure detection circuit supports reliability testing of a memory device by accumulating a sum of data errors in data read from the memory device. The detection circuit compares a plurality of bytes of data read from the memory device against a plurality of bytes of reference data supplied during a test operation. The detection circuit also generates a flag upon detection that the sum of data errors exceeds a threshold number of acceptable data errors.