Bit-Flipping Decoder Handling Defective Bitline Erasures

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Solution Overview

Problem

Existing bit flipping decoders in memory devices have lower error correction capability compared to MinSum algorithm-based decoders, and they inefficiently utilize spare bitlines due to swapping out defective bitlines instead of accounting for their locations during error correction.

Innovation Solution

A bit flipping decoder that treats defective bitline locations as erasures, using all spare bitlines as error correction code parity bits and marking defective bits differently to improve error correction capability without swapping, thereby enhancing the error correction process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If defective bitlines are swapped out using traditional methods, then the decoder can handle defective bits, but spare bitlines are inefficiently utilized and error correction capability remains limited

Engineering Contradiction:
Improveerror correction capabilityVSAvoidspare bitline utilization efficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent changes the parameter of how defective bitlines are handled by treating them as erasures with known locations rather than swapping them out. This allows the decoder to use all spare bitlines as error correction code parity bits, improving both error correction capability and resource utilization efficiency simultaneously

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Instead of the traditional approach of swapping out defective bitlines, the patent inverts the approach by keeping defective bitlines in place and treating them as erasures during decoding. This inversion allows spare bitlines to be fully utilized for error correction, resolving the contradiction between handling defects and resource efficiency

Inventive Principle:
Principle #13The other way round (Inversion)

2Use of energy by moving object

If bit flipping decoder is used instead of MinSum algorithm, then energy consumption is reduced, but error correction capability is lowered

Engineering Contradiction:
Improvedecoder energy consumptionVSAvoiderror correction capability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies local quality by treating defective bitline locations as erasures with special handling in the bit flipping decoder. This localized treatment of defective positions allows the simple bit flipping algorithm to achieve better error correction capability while maintaining low energy consumption, resolving the contradiction between energy efficiency and correction capability

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11398835B1Managing defective bitline locations in a bit flipping decoder
Publication Date: 2022.07.26 MICRON TECHNOLOGY INC
  • US11398835B1 patent drawing
  • US11398835B1 patent drawing
  • US11398835B1 patent drawing

AI summary

Methods, systems, and apparatuses include receiving a codeword stored in a memory device. The codeword has bits from defective bit locations and non-defective bit locations. A syndrome of a current copy of the codeword is determined. Channel information for non-defective bit locations is determined using the current copy of the codeword and the received codeword from the memory device. Energy function values are determined for bits of the codeword using the syndrome of the current copy. Determining the energy function values includes using the channel information for bits in non-defective bit locations and omitting channel information for bits in defective bit locations. One or more bits of the codeword are flipped in response to the energy function values for the one or more bits satisfying a bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.