Bit-Flipping Decoder Check Node Updates for Faster Memory Error Correction
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Solution Overview
Problem
Existing memory systems face challenges in efficiently correcting bit errors with methods like LDPC decoders, which are slow and expensive, necessitating a faster and more economical solution for error correction in memory devices.
Innovation Solution
Implementing a bit-flipping decoder that delays updates of first check node values until specific conditions are met, combined with immediate updates of second check node values, to improve quality of service and reduce power consumption without compromising reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If immediate updates of check node values are implemented in bit-flipping decoders, then correction speed is improved, but power consumption increases and correction accuracy deteriorates
Solution Approach 1:
The patent implements periodic updates of check node values at specific intervals during the decoding process, rather than updating after every single bit flip operation. This periodic update mechanism reduces the frequency of memory access and computation operations, thereby lowering power consumption while still maintaining effective error correction capability.
Solution Approach 2:
The patent dynamically adjusts the update strategy based on the decoding state by maintaining two separate check node value sets: one updated immediately for speed-critical operations and another updated periodically for power-efficient operations. This dynamic approach allows the system to optimize between speed and power consumption based on operational requirements.
2Speed
If immediate updates of check node values are implemented in bit-flipping decoders, then correction speed is improved, but correction accuracy deteriorates
Solution Approach 1:
The patent segments the check node value updates into two distinct sets: first check node values that are updated periodically and second check node values that are updated immediately. This segmentation allows the system to use different update strategies for different operational phases, ensuring both speed and accuracy requirements are met simultaneously.
Solution Approach 2:
By implementing periodic updates of the first check node values at strategically chosen intervals, the patent ensures that correction accuracy is maintained without requiring continuous updates. This periodic mechanism prevents the degradation of correction accuracy while avoiding the overhead of immediate updates after every operation.
3Reliability
If LDPC decoders are used for error correction, then correction power is improved, but processing speed deteriorates and implementation cost increases
Solution Approach 1:
The patent employs a bit-flipping decoder that uses simplified update mechanisms with periodic refreshes of check node values, rather than the complex and computationally intensive LDPC decoder. This approach uses lighter-weight computational objects that are refreshed periodically, achieving acceptable error correction performance with significantly reduced processing complexity and improved speed.
Solution Approach 2:
The periodic update strategy allows the bit-flipping decoder to maintain effective error correction capability over multiple iterations without requiring the continuous heavy computation of LDPC decoders. This periodic refresh mechanism enables the simpler bit-flipping approach to achieve comparable reliability with much higher processing speed.
Data Source
AI summary
This application is directed to error correction for data stored in a memory device. In response to a request to validate a block of data, the memory device identifies a set of check nodes corresponding to a set of variable nodes that represent the block of data. First check node values of the check nodes are determined based on the block of data, and stored in first registers. The memory device implements a plurality of iterations of error correction by flipping a subset of variable nodes successively during each iteration; determining second check node values of the check nodes; and updating the first check node values stored in the first registers based on the second check node values once in each of a first set of iterations and successively with flipping of each variable node in a second set of iterations following the first set of iterations.