Bit-Flipping ECC Decoder With Dynamic Thresholds for Error Asymmetry
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Solution Overview
Problem
Bit-flipping ECC decoders in non-volatile data storage devices face reduced correction capability and increased latency and power consumption due to variance in memory dies, blocks, or pages, as they use a fixed channel model that diverges from actual error profiles.
Innovation Solution
A system and method for dynamically selecting thresholds for bit-flipping ECC decoders based on actual error counts and bit counts associated with decoded data, allowing different thresholds for bits with different logical values and reliability levels, thereby improving decoding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single set of fixed thresholds is used for bit-flipping decisions, then the decoder structure remains simple and fast, but correction capability deteriorates due to variance in memory dies, blocks, or pages
Solution Approach 1:
The patent implements dynamic threshold selection by determining a first threshold based on a first bit error rate for bits with a first logical value and a second threshold based on a second bit error rate for bits with a second logical value. These thresholds are dynamically adjusted based on measured error rates from actual decoded data, allowing the decoder to adapt to varying error conditions across different memory dies, blocks, or pages while maintaining the speed advantages of bit-flipping decoding.
Solution Approach 2:
The patent changes the threshold parameters based on measured bit error rates. By monitoring the actual error rates for different logical values in decoded data and adjusting the thresholds accordingly, the system optimizes correction capability for specific memory regions without requiring a complete redesign of the decoder architecture, thus maintaining productivity while improving reliability.
2Reliability
If multiple sets of thresholds are used to account for error asymmetry, then correction capability improves, but device complexity increases
Solution Approach 1:
The patent applies different thresholds locally based on the logical value of individual bits. Instead of using a single global threshold, the system determines a first threshold for bits with a first logical value and a second threshold for bits with a second logical value, allowing each bit to be evaluated with the most appropriate threshold for its specific error characteristics.
Solution Approach 2:
The system uses feedback from actual decoded data to determine bit error rates for different logical values, then uses these measured error rates to select appropriate thresholds. This feedback mechanism allows the decoder to adapt to actual error conditions without requiring complex pre-characterization or multiple fixed threshold sets for all possible conditions.
3Reliability
If dynamic threshold selection based on measured error rates is implemented, then correction capability and decoding accuracy improve, but computational overhead and latency increase
Solution Approach 1:
The patent performs preliminary measurement of bit error rates during initial decoding operations or training phases, then uses these pre-measured error rates to select thresholds for subsequent decoding operations. This preliminary action allows the system to cache threshold values that can be quickly applied without repeated measurement overhead during time-critical decoding operations.
Solution Approach 2:
The decoder performs self-characterization by measuring its own bit error rates on actual decoded data and automatically adjusting its thresholds accordingly. This self-service approach eliminates the need for external calibration or complex control systems, allowing the decoder to adapt to its specific operating conditions with minimal overhead.
Data Source
AI summary
A device includes a comparator configured to select a first threshold in response to a value of a variable node indicating a first logical value and to select a second threshold in response to the value of the variable node indicating a second logical value. The device also includes a variable node update circuit configured to adjust the value of the variable node in response to a number of unsatisfied check nodes associated with the variable node satisfying the selected threshold.