Bit Flipping Order Adaptation for Iterative Error Correction

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Solution Overview

Problem

Bit Flipping (BF) decoders in memory subsystems suffer from lower error correction capability compared to MinSum Algorithm (MSA)-based decoders, leading to false flips and increased codeword error rates, which hinders their deployment in energy-conscious applications.

Innovation Solution

Implementing a dynamic bit flipping order for iterative error correction, where the order is modified based on bit flipping criteria and energy functions to reduce false flips, allowing BF decoders to approach the error correction capability of MSA-based decoders.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If Bit Flipping decoders are used for error correction, then energy consumption is reduced, but error correction capability deteriorates leading to false flips and increased codeword error rates

Engineering Contradiction:

Improveenergy consumptionVSAvoiderror correction capability

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent implements dynamic bit flipping order where the processing device changes the order of bit traversal based on detected stall patterns. The system transitions from a static flipping order to a dynamic one that adapts during iterative error correction, allowing BF decoders to maintain low energy consumption while improving error correction capability by avoiding false flips on vulnerable bits

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of bit flipping order from fixed to variable. By detecting stall patterns and identifying vulnerable bits, the system modifies the flipping order parameter dynamically, which resolves the contradiction between energy efficiency and error correction capability without requiring a complete switch to higher-energy MSA-based decoders

Inventive Principle:

Principle #35Parameter changes

2Device complexity

If static bit flipping order is used in iterative error correction, then device complexity is reduced, but codeword error rate increases due to false flips on vulnerable bits

Engineering Contradiction:

Improveerror correction algorithm complexityVSAvoidcodeword error rate

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent implements feedback mechanisms where the processing device monitors iterative error correction progress, detects stall patterns, and uses this information to dynamically adjust the bit flipping order. This feedback loop identifies vulnerable bits that cause false flips and modifies the flipping sequence accordingly, reducing codeword error rates while maintaining algorithmic simplicity

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent performs preliminary detection of stall patterns and identification of vulnerable bits before continuing error correction. By anticipating which bits are likely to cause false flips and adjusting the flipping order in advance, the system prevents false flips before they occur, reducing codeword error rates without adding significant complexity

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20220321148A1Dynamic bit flipping order for iterative error correction

Publication Date: 2022.10.06 MICRON TECHNOLOGY INC

AI summary

Methods, systems, and apparatuses include receiving a codeword stored in a memory device. The codeword is error corrected for a first number of iterations. The error correction includes traversing the codeword according to a first order. The codeword is error corrected for a second number of the iterations. The error correction of the codeword during a second iteration from the second number of iterations includes traversing the codeword according to a second order that is different from the first order.