Bit-Flipping Decoder Oscillation Detection in LDPC Memory Decoding
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Solution Overview
Problem
Bit-flipping decoders in non-volatile memory devices often experience oscillations during decoding, leading to failure and reduced throughput due to their inherent unreliability and sensitivity to error patterns, which complicates data integrity in SSDs.
Innovation Solution
Implementing a method to detect oscillations in bit-flipping decoders by computing checksum values and bit flip counts, and then performing subsequent decoding iterations with a randomized order to mitigate oscillations, thereby improving decoding performance and reducing failure rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit-flipping decoder performs multiple decoding iterations to improve error correction capability, then data reliability is improved, but oscillation occurs leading to decoding failure and reduced throughput
Solution Approach 1:
The patent applies preliminary action by detecting oscillation patterns (through checksum and bit-flip count analysis) before the decoder fully fails, then proactively switching to an alternative decoding strategy (different update rule or randomization) to escape the oscillation and continue decoding, thereby maintaining both reliability and throughput
Solution Approach 2:
The patent changes decoding parameters dynamically by monitoring oscillation indicators (checksum values, bit-flip counts) and switching between different decoding approaches (e.g., from deterministic bit-flipping to randomized or alternative update rules) when oscillation is detected, thus resolving the contradiction between reliability and throughput
2Reliability
If bit-flipping decoder uses strong error-correction codes to protect data integrity, then data protection is improved, but extra storage space is required for ECC parity bits
Solution Approach 1:
The patent changes the decoding approach parameters (update rules, processing order) rather than changing the code parameters, allowing the same LDPC code structure to be decoded more effectively through dynamic strategy adjustment, thus maintaining data protection without requiring additional storage space
3Measurement precision
If bit-flipping decoder performs exhaustive decoding iterations to ensure error correction, then decoding accuracy is improved, but decoding time increases
Solution Approach 1:
The patent performs preliminary oscillation detection during the decoding process by analyzing checksum and bit-flip count patterns, allowing early identification of unproductive decoding iterations and timely switching to alternative strategies, thus avoiding unnecessary decoding time while maintaining accuracy
Solution Approach 2:
The patent applies skipping by detecting oscillation patterns and bypassing continued execution of unproductive decoding iterations, instead switching to alternative decoding approaches that escape the oscillation, thereby reducing wasted decoding time while preserving decoding accuracy
Data Source
AI summary
Devices, systems, and methods for detecting and mitigating oscillations in a bit-flipping decoder associated with a non-volatile memory are described. An example method includes receiving a noisy codeword based on a transmitted codeword generated from a low-density parity-check code, performing a first plurality of decoding iterations on the noisy codeword, which comprises performing a message passing algorithm in a first order, computing, based on a completion of the first plurality of decoding iterations, a plurality of checksum values and a plurality of bit flip counts corresponding to the first plurality of decoding iterations, determining that the plurality of checksum values and the plurality of bit flip counts are periodic with a period less than a predetermined threshold, and performing a subsequent decoding iteration on the noisy codeword, the subsequent decoding iteration comprising performing the message passing algorithm in a second order different from the first order.