Bit-Group LDPC Interleaver for 16-Symbol Mapping Under Burst Errors
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 2/15, using 16-symbol mapping, is designed to effectively distribute burst errors by interleaving the LDPC codeword on a bit group basis, with a specific permutation order, and integrated into a BICM device for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in digital broadcast channels cause rapid performance degradation
Solution Approach 1:
The bit interleaver divides the codeword into multiple bit groups and applies different interleaving patterns to different segments. This segmentation allows burst errors to be distributed across multiple code words rather than concentrated in one location, thereby improving error distribution and system reliability
Solution Approach 2:
The interleaver uses different interleaving parameters (such as interleaving depth, pattern, and step size) optimized for specific modulation orders and code rates. By adapting these parameters to match the channel conditions and system configuration, the interleaver effectively mitigates burst errors while maintaining performance
2Reliability
If the bit interleaver is optimized for specific modulation order and code rate parameters, then performance is improved, but the device complexity increases
Solution Approach 1:
The patent defines specific interleaving parameters (such as interleaving factor, block size, and permutation patterns) that are optimized for particular modulation orders and code rates. These parameter sets can be selected based on system configuration, providing performance optimization without requiring a completely different interleaver structure for each case
Solution Approach 2:
The interleaver design allows dynamic selection of interleaving parameters based on the modulation order and code rate being used. This enables the system to adapt to different operating conditions while maintaining a unified interleaver architecture, balancing performance optimization with implementation simplicity
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.