Bit-Group LDPC Interleaver for 64-Symbol Mapping in BICM
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 64800 and code rate of 4/15, using a processor to generate an interleaved codeword on a bit group basis, with a specific permutation order optimized for 64-symbol mapping, effectively distributing burst errors in broadcasting systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in digital broadcast channels cause rapid performance degradation
Solution Approach 1:
The bit interleaver divides the codeword into multiple bit groups and applies different permutation patterns to different segments. This segmentation allows burst errors to be distributed across multiple code blocks rather than concentrated in one location, thereby improving error distribution and system reliability under burst error conditions.
Solution Approach 2:
The patent introduces a two-dimensional interleaving structure by organizing bits into rows and columns, then performing row-wise and column-wise permutations separately. This dimensional transformation effectively disperses burst errors that occur in the time domain across different spatial positions in the interleaved sequence, converting concentrated errors into scattered errors that are easier to correct.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then performance improves, but the device complexity increases
Solution Approach 1:
The patent employs parameter-based permutation patterns where the interleaving sequence is determined by mathematical parameters such as block size, code rate, and modulation order. By changing these parameters, the same interleaver structure can be adapted to different system configurations without redesigning the entire interleaver, thus maintaining performance optimization while controlling complexity through parameterization rather than structural redesign.
Solution Approach 2:
The designed bit interleaver uses a universal permutation framework that can handle multiple modulation orders (QPSK, 16-QAM, 64-QAM) and various LDPC code rates (1/2, 2/3, 3/4, 4/5, 4/6, 4/7, 4/8) through a single unified structure. This multi-functionality is achieved by adjusting permutation parameters rather than creating separate interleavers for each configuration, thereby reducing overall system complexity while maintaining optimized performance across different operating conditions.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.