Bit-Group LDPC Interleaving for Burst-Error Robust 64-Symbol Mapping
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 64800 and code rate of 5/15, using a specific permutation order for bit group-based interleaving, optimized for 64-symbol mapping, to effectively distribute burst errors in BICM systems, particularly for next-generation broadcasting like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The bit interleaver divides the codeword into multiple bit groups and applies different permutation orders to different segments. This segmentation allows the system to handle burst errors more effectively by distributing them across different segments, thereby improving error correction performance without requiring a completely complex redesign of the entire interleaver structure.
Solution Approach 2:
The patent employs multiple permutation orders as configurable parameters within the interleaver design. By changing the permutation order parameter based on channel conditions and error patterns, the interleaver can adapt to different burst error scenarios, improving reliability while maintaining a relatively simple base structure that doesn't require complete redesign for different conditions.
2Reliability
If the bit interleaver is optimized for specific modulation order and code rate, then performance is improved for those parameters, but adaptability to other parameters decreases
Solution Approach 1:
The bit interleaver is designed with a universal structure that can handle multiple modulation orders and code rates. By incorporating multiple permutation orders and allowing configuration based on the specific modulation and coding parameters being used, the interleaver achieves optimized performance for each parameter combination while maintaining a single versatile design that doesn't require separate interleavers for different scenarios.
Solution Approach 2:
The interleaver employs dynamic permutation orders that can be selected and changed based on the current modulation order and code rate being used. This dynamic adaptation allows the system to optimize performance for the specific parameters in use while maintaining the ability to switch between different parameter sets, thereby achieving both specialized optimization and broad adaptability within a single flexible structure.
Data Source
AI summary
A bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.